Apparatus including soi cmos transistor pair

An apparatus, comprising:

• a memory cell array region;
• and
• a peripheral region including a silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) transistor pair, the SOI CMOS transistor pair including an SOI P-channel metal-oxide-silicon (PMOS) transistor and an SOI N-channel MOS (NMOS) transistor, wherein
• each of the SOI PMOS transistor and the SOI NMOS transistor includes a buried oxide (BOX) layer in a semiconductor substrate and an SOI layer on the BOX layer,
• the SOI layer of the SOI PMOS transistor includes a silicon germanium (SiGe) layer, and the SOI layer and the SiGe layer together have a first thickness such that a first depletion layer when formed fills the SOI layer and the SiGe layer between a PMOS transistor gate and the BOX layer and between PMOS transistor source/drain regions, and
• the SOI layer of the SOI NMOS transistor has a second thickness such that a second depletion layer when formed fills the SOI layer between an NMOS transistor gate and the BOX layer and between NMOS transistor source/drain regions.

An apparatus, comprising:

• a silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) transistor pair on a first semiconductor substrate;
• and
• a memory cell array on a second semiconductor substrate,
• wherein the SOI CMOS transistor pair includes:
• a buried oxide (BOX) layer in the first semiconductor substrate;
• an SOI layer on the BOX layer;
• and
• a gate stack structure on the SOI layer, and
• wherein the SOI layer has a thickness such that a depletion layer when formed in the SOI layer fills the SOI layer between the gate stack structure and the BOX layer and between source/drain regions.