Cell architecture including signal line tracks on front side and back side of cell

A cell architecture comprising:

• 1st to 5th frontside signal tracks extended in a 1st direction and arranged in a 2nd direction intersecting the 1st direction on a front side of a semiconductor cell, and
• at least one signal line provided in at least one of the 2nd to 4th frontside signal tracks and connected to at least one front-end-of-line (FEOL) structure or at least one middle-of-line (MOL) structure in the semiconductor cell,
• wherein at least the 2nd to 4th frontside signal tracks are disposed at a same level in a 3rd direction intersecting the 1st direction and the 2nd direction,
• wherein no other frontside signal track is disposed between the 1st to 5th frontside signal tracks, and
• wherein the 1st frontside signal track overlaps a 1st boundary of the semiconductor cell in a 3rd direction intersecting the 1st direction and the 2nd direction, and the 5th frontside signal track overlaps a 2nd boundary of the semiconductor cell in the 3rd direction, the 2nd boundary facing the 1st boundary in the 2nd direction.

A cell architecture comprising

• a plurality of transistors configured to perform a logic function within a semiconductor cell;
• three or less frontside signal tracks with a plurality of signal lines therein, the plurality of signal lines being connected to at least one of the plurality of transistors, wherein the frontside signal tracks are at a same level on a front side of the semiconductor cell inside a 1st boundary and a 2nd boundary of the semiconductor cell, and extended in a 1st direction in parallel with the 1st boundary or the 2nd boundary, the 1st boundary facing the 2nd boundary in a 2nd direction intersecting the st direction;
• and
• one or more backside signal tracks with at least one backside signal line therein, the at least one signal line connecting at least two of the plurality of transistors.