US 2026/0040658 A1Published application

Semiconductor device

AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation

InventorsShunsuke ASABA, Hiroshi KONO

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Abstract

A semiconductor device of embodiments includes an element region, a termination region, and an intermediate region between the element region and the termination region. The element region includes: a silicon carbide layer having a first conductive type silicon carbide region and a second conductive type of silicon carbide regions; and a gate electrode. The intermediate region includes a silicon carbide layer having a second conductive type silicon carbide region outside the second conductive type silicon carbide regions. The width of the second conductive type silicon carbide region in the intermediate region is equal to or more than 0.5 times and equal to or less than 3 times the width of the second conductive type silicon carbide region in the element region.

Claims20

Dependent claims

A semiconductor device, comprising:

an element region;
a termination region surrounding the element region;
and
an intermediate region provided between the element region and the termination region and surrounding the element region,
wherein the element region includes:
a first electrode;
a second electrode;
a gate electrode;
a silicon carbide layer provided between the first electrode and the second electrode, having a first face on the first electrode side and a second face on the second electrode side, and including:
a first silicon carbide region of a first conductive type having a first region, a second region provided between the first region and the first face and having a higher first conductive type impurity concentration than the first region, a first portion in contact with the first face and facing the gate electrode, and a second portion in contact with the first face and in contact with the first electrode;
a second silicon carbide region of a second conductive type provided between the second region and the first face and electrically connected to the first electrode;
a third silicon carbide region of the second conductive type provided between the second region and the first face, provided on the intermediate region side of the second silicon carbide region, and electrically connected to the first electrode;
a fourth silicon carbide region of the second conductive type provided between the second region and the first face, provided between the second silicon carbide region and the third silicon carbide region, facing the gate electrode, and electrically connected to the first electrode;
a fifth silicon carbide region of the second conductive type provided between the second region and the first face, provided between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode, and electrically connected to the first electrode;
a sixth silicon carbide region of the second conductive type provided between the second region and the first face, provided between the third silicon carbide region and the fourth silicon carbide region, and having a depth smaller than a depth of the third silicon carbide region and a depth of the fourth silicon carbide region;
and
a seventh silicon carbide region of the first conductive type provided between the fifth silicon carbide region and the first face and electrically connected to the first electrode;
and
a gate insulating layer provided between the gate electrode and the fifth silicon carbide region and between the gate electrode and the first portion,
the termination region includes:
a wiring layer electrically connected to the first electrode;
the second electrode;
and
the silicon carbide layer including the first silicon carbide region having a third portion in contact with the first face and in contact with the wiring layer and an eighth silicon carbide region of the second conductive type provided between the first silicon carbide region and the first face, electrically connected to the wiring layer, and having a smaller depth than the third silicon carbide region, and
the intermediate region includes:
the second electrode;
and
the silicon carbide layer including:
the first silicon carbide region;
a ninth silicon carbide region of the second conductive type provided between the first silicon carbide region and the first face, electrically connected to the first electrode, in contact with the third silicon carbide region and the eighth silicon carbide region, and having a smaller depth than the third silicon carbide region;
and
a tenth silicon carbide region of the second conductive type provided between the first silicon carbide region and the ninth silicon carbide region, a first width of the tenth silicon carbide region in a first direction parallel to the first face being equal to or more than 0.5 times and equal to or less than 3 times a second width of the fourth silicon carbide region in the first direction, and a first distance in the first direction between the tenth silicon carbide region and the third silicon carbide region being equal to or more than 0.5 times and equal to or less than 3 times a second distance in the first direction between the fourth silicon carbide region and the fifth silicon carbide region.

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Dependencies are inferred from the claim text.

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Abstract

A semiconductor device, comprising:

an element region;
a termination region surrounding the element region;
and
an intermediate region provided between the element region and the termination region and surrounding the element region,
wherein the element region includes:
a first electrode;
a second electrode;
a gate electrode;
a silicon carbide layer provided between the first electrode and the second electrode, having a first face on the first electrode side and a second face on the second electrode side, and including:
a first silicon carbide region of a first conductive type having a first region, a second region provided between the first region and the first face and having a higher first conductive type impurity concentration than the first region, a first portion in contact with the first face and facing the gate electrode, and a second portion in contact with the first face and in contact with the first electrode;
a second silicon carbide region of a second conductive type provided between the second region and the first face and electrically connected to the first electrode;
a third silicon carbide region of the second conductive type provided between the second region and the first face, provided on the intermediate region side of the second silicon carbide region, and electrically connected to the first electrode;
a fourth silicon carbide region of the second conductive type provided between the second region and the first face, provided between the second silicon carbide region and the third silicon carbide region, facing the gate electrode, and electrically connected to the first electrode;
a fifth silicon carbide region of the second conductive type provided between the second region and the first face, provided between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode, and electrically connected to the first electrode;
a sixth silicon carbide region of the second conductive type provided between the second region and the first face, provided between the third silicon carbide region and the fourth silicon carbide region, and having a depth smaller than a depth of the third silicon carbide region and a depth of the fourth silicon carbide region;
and
a seventh silicon carbide region of the first conductive type provided between the fifth silicon carbide region and the first face and electrically connected to the first electrode;
and
a gate insulating layer provided between the gate electrode and the fifth silicon carbide region and between the gate electrode and the first portion,
the termination region includes:
a wiring layer electrically connected to the first electrode;
the second electrode;
and
the silicon carbide layer including the first silicon carbide region having a third portion in contact with the first face and in contact with the wiring layer and an eighth silicon carbide region of the second conductive type provided between the first silicon carbide region and the first face, electrically connected to the wiring layer, and having a smaller depth than the third silicon carbide region, and
the intermediate region includes:
the second electrode;
and
the silicon carbide layer including:
the first silicon carbide region;
a ninth silicon carbide region of the second conductive type provided between the first silicon carbide region and the first face, electrically connected to the first electrode, in contact with the third silicon carbide region and the eighth silicon carbide region, and having a smaller depth than the third silicon carbide region;
and
a tenth silicon carbide region of the second conductive type provided between the first silicon carbide region and the ninth silicon carbide region, a first width of the tenth silicon carbide region in a first direction parallel to the first face being equal to or more than 0.5 times and equal to or less than 3 times a second width of the fourth silicon carbide region in the first direction, and a first distance in the first direction between the tenth silicon carbide region and the third silicon carbide region being equal to or more than 0.5 times and equal to or less than 3 times a second distance in the first direction between the fourth silicon carbide region and the fifth silicon carbide region.

29 more elements