Method of manufacturing integrated circuit device

A method of manufacturing an integrated circuit device, the method comprising:

• alternately stacking a plurality of sacrificial layers and a plurality of channel layers layer by layer on a first surface of a substrate including the first surface and a second surface opposite to the first surface;
• etching a portion of each of the plurality of sacrificial layers and the plurality of channel layers to divide the plurality of channel layers into a plurality of nanosheet stacks;
• forming a source/drain region between the plurality of nanosheet stacks;
• removing the plurality of sacrificial layers and forming a first gate structure including a gate dielectric layer and a gate line in an area from which the plurality of sacrificial layers have been removed;
• etching a portion of the second surface of the substrate in an area where the first gate structure is arranged in a plan view to form an opening in the substrate and forming a backside insulating structure in the opening including a lower surface facing the first surface of the substrate and an upper surface facing the second surface of the substrate;
• etching the substrate so that at least a portion of the source/drain region is exposed;
• and
• forming a liner on an exposed surface of the source/drain region and on at least a portion of a side surface of the substrate and forming a backside contact on the liner.

A method of manufacturing an integrated circuit device, the method comprising:

• forming a placeholder, a source/drain region, and a first gate structure including a gate dielectric layer and a gate line on a first surface of a substrate including the first surface and a second surface opposite to the first surface;
• etching a portion of the second surface of the substrate in an area where the first gate structure is arranged in a plan view to form an opening in the substrate and forming a backside insulating structure in the opening;
• forming a backside insulating layer on an upper surface of the backside insulating structure and the second surface of the substrate, and an interlayer insulating layer on the backside insulating layer;
• removing a portion of the interlayer insulating layer and the backside insulating layer to expose a portion of the substrate and forming a hole in the substrate so that at least a portion of the placeholder is exposed;
• removing the placeholder and forming a silicide liner on a side surface and a lower surface of the hole, to a vertical level lower than a vertical level of the backside insulating layer where the first surface of the substrate provides a base reference plane and the second surface of the substrate is above the first surface of the substrate, in a space from which the placeholder has been removed;
• and
• forming a backside contact in a space bordered by the liner and an empty space in the interlayer insulating layer.