Split double gate transistor and method for manufacturing the same

A method for manufacturing a split double gate transistor, comprising processes of:

• forming a first fin including a plurality of gate metal layers and a plurality of sacrificial layers that are stacked alternately on a substrate;
• removing the plurality of sacrificial layers from a portion of the first fin;
• sequentially forming a first gate insulating layer, a channel layer and a protection layer on an exposed portion of each of the plurality of gate metal layers;
• patterning the first fin, the first gate insulating layer, the channel layer and the protection layer to form a second fin;
• patterning the second fin to form a plurality of first recesses on a first side and a second side and a plurality of second recesses on a third side and a fourth side;
• forming a plurality of inner spacer layers to fill in the plurality of first recesses and the plurality of second recesses;
• forming a first gate component connected electrically to the plurality of gate metal layers on the first side, a drain component connected electrically to the channel layer on the third side, and a source component connected electrically to the channel layer on the fourth side;
• removing a portion of the plurality of inner spacer layers and the protection layer from the second side, to expose each of the plurality of gate metal layers, the first gate insulating layer, the channel layer, and each of the plurality of inner spacer layers that are not removed;
• and
• sequentially forming a second gate insulating layer, a plurality of gate connectors and a second gate component, on each of the plurality of gate metal layers, the first gate insulating layer and the channel layer that are exposed, and on each of the plurality of inner spacer layers that are not removed.