III-Nitride Transistors with Field Plate and Methods of Fabrication
OwnerHal Emmer, Sangmin Leeinventors
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Abstract
A new semiconductor structure and method of fabrication is disclosed. The semiconductor structure includes a source-connected field plate, which in some embodiments, is located at least as close to the barrier layer as the gate field plate, if present. The source-connected field plate is formed by patterning the dielectric layer to create a cavity in which metal will be deposited to form the source-connected field plate. In some embodiments, there may be multiple source-connected field plates, which are each at a different distance from the barrier layer. These multiple source-connected field plates may be created using a single metal deposition process.
Claims20
A semiconductor transistor for use in a III-Nitride (III-N) semiconductor device, comprising:
- a channel layer;
- a barrier layer located on the channel layer in a height direction;
- a dielectric layer disposed on the barrier layer;
- a source electrode and a drain electrode, wherein a direction between the source electrode and the drain electrode is a length direction;
- a gate electrode disposed between the source electrode and the drain electrode in the length direction and extending in a width direction, wherein a top portion of the gate electrode comprises a gate field plate disposed on a top surface of the dielectric layer and extending in the length direction;
- and
- a source-connected field plate disposed between the gate electrode and the drain electrode in the length direction, wherein a bottom surface of the source-connected field plate is a same distance or closer to the barrier layer than a bottom surface of the gate field plate.
A method of fabricating a III-Nitride semiconductor transistor, comprising:
- creating an assembly including a substrate, buffer layer, channel layer and a barrier layer;
- depositing a first dielectric sublayer on the barrier layer;
- depositing a second dielectric sublayer on the first dielectric sublayer;
- patterning and etching the second dielectric sublayer to create a cavity;
- and
- depositing metal into the cavity to form a source-connected field plate.
A method of fabricating a III-Nitride semiconductor transistor, comprising:
- creating an assembly including a substrate, buffer layer, channel layer and a barrier layer;
- depositing a dielectric layer on the barrier layer;
- patterning and etching the dielectric layer to create a gate cavity;
- and
- depositing metal into the gate cavity to form a gate electrode and on top of the dielectric layer to form a source-connected field plate, wherein the gate electrode and the source-connected field plate are created by a same metallization step.
Dependencies are inferred from the claim text.