Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device that can be easily miniaturized is provided. A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is positioned above the first conductive layer and includes a first opening reaching the first conductive layer. The second conductive layer is positioned above the first insulating layer. The semiconductor layer is in contact with the second conductive layer and a side surface of the first insulating layer and a top surface of the first conductive layer in the first opening. The third insulating layer is in contact with a top surface of the first insulating layer and the semiconductor layer in the first opening. The second insulating layer is positioned above the third insulating layer and includes a second opening reaching the third insulating layer in a position overlapping the first opening. The third conductive layer is provided to fill the second opening and the first opening.

Dependencies are inferred from the claim text.