Three-dimensional memory devices having semiconductor assemblies bonded by bonding layer and methods for forming the same

A three-dimensional (3D) memory device, comprising:

• a first semiconductor assembly comprising:
• a first array structure comprising a first stack comprising interleaved first conductive layers and first dielectric layers in a first direction;
• and
• a first periphery structure comprising a first peripheral circuit;
• a second semiconductor assembly comprising:
• a second array structure comprising a second stack comprising interleaved second conductive layers and second dielectric layers in the first direction;
• and
• a second periphery structure comprising a second peripheral circuit;
• a first interconnect structure and a second interconnect structure located at a side of the first semiconductor assembly away from the second semiconductor assembly in the first direction;
• a first contact structure extending in the first semiconductor assembly in the first direction, wherein the first contact structure is connected with the first interconnect structure and the first peripheral circuit;
• and
• a second contact structure extending in the first semiconductor assembly and the second semiconductor assembly in the first direction, wherein the second contact structure is connected with the second interconnect structure and the second peripheral circuit.

A three-dimensional (3D) memory device, comprising:

• a first array structure comprising:
• a first stack comprising interleaved first conductive layers and first dielectric layers;
• a first semiconductor layer;
• a first channel structure extending through the first stack and into the first semiconductor layer in a first direction;
• and
• a first source contact structure connected to the first semiconductor layer, wherein the first semiconductor layer is between the first source contact structure and the first stack in the first direction;
• a second array structure comprising a second stack comprising interleaved second conductive layers and second dielectric layers, wherein the first source contact structure is between the first semiconductor layer and the second array structure in the first direction.