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US 2026/0040569 A1Published application
Three-dimensional memory device with tubular channels and integrated access transistors and method of making the same
AssigneeSanDisk Technologies LLC
InventorsAdarsh RAJASHEKHAR, Senaka KANAKAMEDALA, Joyeeta NAG, Johann ALSMEIER
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Abstract
A device structure includes a three-dimensional array of unit cells. Each of the unit cells includes an access field effect transistor including a horizontally-extending semiconductor channel, a first gate dielectric, and a first gate electrode, and a memory field effect transistor including a tubular-portion-containing channel, a second gate dielectric, and a second gate electrode. The second gate dielectric includes a memory dielectric material having at least two programmable states.
Claims20
A device structure comprising a three-dimensional array of unit cells, wherein each of the unit cells comprises:
- an access field effect transistor comprising a horizontally-extending semiconductor channel, a first gate dielectric, and a first gate electrode;
- and
- a memory field effect transistor comprising a tubular-portion-containing channel, a second gate dielectric, and a second gate electrode,
- wherein the second gate dielectric comprises a memory dielectric material having at least two programmable states.
1 more element
A method of forming a device structure, comprising:
- forming a three-dimensional array of horizontally-extending semiconductor rails supported by a three-dimensional array of horizontally-extending sacrificial rails;
- removing first portions of horizontally-extending sacrificial rails to expose sidewalls and horizontal surfaces of first portions of the horizontally-extending semiconductor rails;
- depositing a first gate dielectric material and a first gate electrode material around the first portions of the horizontally-extending semiconductor channels;
- removing second portions of horizontally-extending sacrificial rails to expose sidewalls and horizontal surfaces of second portions of the horizontally-extending semiconductor rails;
- forming tubular-portion-containing channels on the second portions of the horizontally-extending semiconductor rails;
- depositing a second gate dielectric material and a second gate electrode material around the tubular-portion-containing channels;
- and
- patterning the first gate electrode material, the second gate electrode material, the first gate dielectric material, and the second gate dielectric material, wherein patterned portions of the first gate electrode material comprise first word lines, patterned portions of the second gate electrode material comprise second word lines, patterned portions of the first gate dielectric material comprise first gate dielectrics, and patterned portions of the second gate dielectric material comprise second gate dielectrics.
5 more elements
A method of forming a device structure, comprising:
- forming a three-dimensional array of horizontally-extending semiconductor rails supported by a three-dimensional array of horizontally-extending sacrificial rails;
- removing first portions of horizontally-extending sacrificial rails to expose sidewalls and horizontal surfaces of first portions of the horizontally-extending semiconductor rails;
- depositing a first gate dielectric material and a first gate electrode material around the first portions of the horizontally-extending semiconductor channels;
- removing second portions of horizontally-extending sacrificial rails to expose sidewalls and horizontal surfaces of second portions of the horizontally-extending semiconductor rails;
- depositing a second gate dielectric material and a second gate electrode material around the second portions of the horizontally-extending semiconductor channels;
- forming elongated cavities by removing the second portions of the horizontally-extending semiconductor rails;
- forming tubular-portion-containing channels in the elongated cavities on surfaces of the second gate dielectric material;
- and
- patterning the first gate electrode material, the second gate electrode material, the first gate dielectric material, and the second gate dielectric material, wherein patterned portions of the first gate electrode material comprise first word lines, patterned portions of the second gate electrode material comprise second word lines, patterned portions of the first gate dielectric material comprise first gate dielectrics, and patterned portions of the second gate dielectric material comprise second gate dielectrics.
6 more elements
Dependencies are inferred from the claim text.