Memory device including capacitive sensing circuit

An apparatus comprising:

• a data line;
• memory cells including associated memory cell pillars;
• a first conductive connection coupled to the memory cell pillars;
• a first transistor including a first terminal coupled to the data line, a second terminal coupled to the first conductive connection, and a first gate;
• a second transistor including a first terminal of the second transistor coupled to the data line, a second terminal of the second transistor, and a second gate;
• a third transistor including a first terminal of the third transistor, a second terminal of the third transistor coupled to the second terminal of the second transistor, and a third gate coupled to the first conductive connection;
• a fourth transistor including a first terminal coupled to the first terminal of the third transistor, a second terminal, and a fourth gate;
• a second conductive connection coupled to the first gate;
• a third conductive connection coupled to the second gate and the fourth gate;
• and
• a fourth conductive connection coupled to the first gate.

A method comprising:

• a first conductive region;
• and located between the first conductive region and the tiers of memory cells;
• tiers of memory cells;
• memory cell pillars extending through the tiers of memory cells;
• forming a first conductive region and a first additional conductive region on a first level of a memory device such that the first conductive region is coupled to memory cell pillars associated with tiers of memory cells;
• forming additional conductive regions on a second level of the memory device such that the additional conductive regions are separated from each other;
• forming conductive contacts over the first conductive region, the first additional conductive region, and one of the additional conductive regions;
• forming semiconductor structures separated from each other such that each of the semiconductor structures is formed over a respective conductive contacts of the conductive contacts, wherein the semiconductor structures are part of transistors of a sensing circuit of the memory device;
• forming additional conductive contacts such that each of the additional conductive contacts is over a respective semiconductor structure of the semiconductor structures;
• and
• forming a second conductive region and a second additional conductive region on a third level of a memory device such that the semiconductor structures are between the first and second levels and such that the second conductive region is coupled to first conductive contacts included in the additional conductive contacts, and the second additional conductive region is coupled to second conductive contacts included in the additional conductive contacts.