Plug for protection of backside source formation of vertical planar memory cells

A method, comprising:

• forming a stack comprising a plurality of oxide layers and a plurality of metal layers, the stack comprising a first level and a second level, wherein the stack comprises a first cavity that passes through at least a portion of the first level of the stack, the first cavity having a first width, wherein the stack comprises a second cavity that passes through at least a portion of the second level of the stack, the second cavity having a second width that is greater than the first width, and wherein the stack comprises a recess within a first oxide layer of the plurality of oxide layers of the second level of the stack, a third width of the second cavity at the first oxide layer greater than the first width and the second width based at least in part on the recess;
• depositing layers of materials within the first cavity, the second cavity, and the recess, the materials comprising a protective liner, a storage material, and a second protective liner, wherein the second cavity has the second width throughout the second level of the stack after depositing the layers of the materials;
• depositing, after depositing the layers of materials, a conductive material within the first cavity and the second cavity, wherein the conductive material forms a plug within the first cavity;
• and
• etching the conductive material in the second level of the stack to form a plurality of bit line structures that extend from the plug through the second level of the stack, wherein each bit line structure of the plurality of bit line structures is physically isolated from other bit line structures within the second level of the stack based at least in part on etching the conductive material in the second level of the stack.

A method, comprising:

• forming a stack comprising a plurality of oxide layers and a plurality of metal layers within a first level and a second level, wherein the stack comprises a first cavity that passes through the first level of the stack, the first cavity having a first width, wherein the stack comprises a second cavity that passes through the second level of the stack, the second cavity having a second width that is greater than the first width, and wherein the stack comprises a recess within a first oxide layer of the plurality of oxide layers of the second level of the stack, a third width of the second cavity at the first oxide layer greater than the first width and the second width based at least in part on the recess;
• depositing a sacrificial material within the first cavity;
• depositing, based at least in part on depositing the sacrificial material, a separation material within the recess and the second cavity;
• etching the separation material to form a plurality of U-shaped separation material segments within the second level, wherein each U-shaped separation material segment of the plurality of U-shaped separation material segments is physically isolated from other U-shaped separation material segments within the second level based at least in part on etching the separation material;
• and
• depositing, after etching the separation material and removing the sacrificial material from the first level of the stack, a conductive material within the first cavity and remaining portions of the second cavity that are between the plurality of U-shaped separation material segments, wherein the conductive material forms a plug within the first cavity and a plurality of bit line structures that extend from the plug through the second level of the stack, wherein each bit line structure of the plurality of bit line structures is physically isolated from other bit line structures of the plurality of bit line structures within the second level by one or more U-shaped separation material segments of the plurality of U-shaped separation material segments.