Curved plug for protection of backside source formation of vertical planar memory cells

A method, comprising:

• forming a first level of a stack comprising a plurality of oxide layers and at least one layer of sacrificial material;
• removing a first portion of oxide material from a first oxide layer of the plurality of oxide layers of the first level of the stack to form a first cavity comprising at least one curved sidewall;
• removing, via the first cavity, a second portion of the oxide material from the first oxide layer, a second oxide layer, or both, and a third portion of sacrificial material from the at least one layer of sacrificial material, wherein removing the second portion of the oxide material and the third portion of the sacrificial material forms a second cavity that extends beneath the first cavity relative to a substrate, wherein a width of the first cavity is greater than a width of the second cavity;
• forming a sacrificial plug within the second cavity and the first cavity, wherein the sacrificial plug comprises a sacrificial plug material that is planar with a top surface of the first level of the stack;
• and
• forming, above the first level of the stack comprising the sacrificial plug, a second level of the stack comprising a second plurality of oxide layers and a plurality of sacrificial material layers.

An apparatus, comprising:

• a substrate;
• a stack comprising a plurality of oxide layers and a plurality of metal layers, the stack comprising a first level and a second level, the first level positioned between the substrate and the second level in a first direction;
• a plug passing through the first level of the stack, wherein the plug extends, in the first direction, along a first axis, the plug comprising a conductive material;
• a plurality of bit line structures extending from the plug through the second level of the stack, wherein each bit line structure of the plurality of bit line structures is coupled with the plug within a respective contact region and is physically isolated from other bit line structures of the plurality of bit line structures within other regions different from the respective contact region, and wherein each bit line structure of the plurality of bit line structures comprises:
• a first segment that extends, in the first direction, along a second axis through the second level of the stack, the second axis offset from the first axis in a second direction different from the first direction;
• a second segment that curves away from the plug in the first direction and the second direction;
• and
• a third segment that curves between the second segment and the first segment, wherein the third segment is in contact with the first segment and the second segment;
• and
• a plurality of memory cells positioned in the second level of the stack, each memory cell of the plurality of memory cells positioned between a respective memory layer of the plurality of metal layers and a respective first segment of each bit line structure of the plurality of bit line structures.