Semiconductor devices and data storage systems including the same

A semiconductor device, comprising:

• a plate layer;
• gate electrodes including first gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer on the plate layer and a second gate electrode on the first gate electrodes;
• a first channel structure extending through the first gate electrodes in the first direction, and including a first channel layer;
• a second channel structure extending through the second gate electrode, and including a second channel layer electrically connected to the first channel layer;
• a channel connection portion on an uppermost surface of the first channel structure and electrically connecting the first channel layer to the second channel layer;
• and
• a horizontal insulating layer extending between an uppermost first gate electrode among the first gate electrodes and the second gate electrode,
• wherein the horizontal insulating layer is on a level different from a level of the channel connection portion in the first direction, and
• wherein the channel connection portion covers a portion of a lower surface of the second channel structure and exposes a portion of the lower surface of the second channel structure.

A data storage system, comprising:

• a semiconductor device storage device including a first semiconductor device structure including circuit devices, a second semiconductor device structure on the first semiconductor device structure, and an input/output pad electrically connected to the circuit devices;
• and
• a controller electrically connected to the semiconductor device storage device through the input/output pad and configured to control the semiconductor device storage device, wherein the second semiconductor device structure includes:
• a plate layer;
• gate electrodes including first gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer on the plate layer and a second gate electrode on the first gate electrodes;
• a first channel structure extending through the first gate electrodes in the first direction, and including a first channel layer;
• a second channel structure extending through the second gate electrode, and including a second channel layer electrically connected to the first channel layer;
• a channel connection portion on an uppermost surface of the first channel structure and electrically connecting the first channel layer to the second channel layer;
• and
• a horizontal insulating layer extending between an uppermost first gate electrode among the first gate electrodes and the second gate electrode,
• wherein an upper surface of the horizontal insulating layer is on a level lower than a level of the uppermost surface of the first channel structure in the first direction where the upper surface of the plate layer provides a base reference plane.