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US 2026/0040535 A1Published application
Wordline contact isolation structure and method
AssigneeMicron Technology, Inc.
InventorsCollin Howder, Andrew L. Li, Jordan D. Greenlee
Life of this patent
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Abstract
Devices and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include interconnect structures with lateral isolation structures around a vertical conductor. Devices and methods are shown where the isolation structures are located with a staircase configuration in a memory device with an array of vertical memory strings.
Claims20
A memory device, comprising;
- a stack of alternating dielectric layers and conductor layers;
- a number of memory cells formed within the stack of alternating dielectric layers and conductor layers;
- a vertical conductor passing from a top level of the stack to at least a selected conductor layer from the stack;
- a lateral connection between a location along the vertical conductor and the selected conductor layer from the stack;
- and
- a lateral isolation structure around the vertical conductor adjacent to at least one other conductor layer from the stack, wherein the lateral isolation structure includes a dielectric material having a lower dielectric constant than 4.0.
3 more elements
A memory device, comprising;
- a stack of alternating dielectric layers and conductor layers;
- a number of memory cells formed within the stack of alternating dielectric layers and conductor layers;
- vertical conductor passing from a top level of the stack to at least a selected conductor layer from the stack;
- a lateral connection between a location along the vertical conductor and the selected conductor layer from the stack;
- and
- a lateral isolation structure around the vertical conductor adjacent to at least one other conductor layer from the stack, wherein the lateral isolation structure includes modified silicon oxide to provide a lower dielectric constant than silicon oxide.
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A method of forming a memory device, comprising;
- forming a staircase in a stack of alternating dielectric layers and placeholder layers;
- forming an etch selective layer on a tread of the staircase;
- filling the staircase with dielectric material to a top surface of the stack;
- forming a vertical passage between the top surface of the stack and a bottom of the stack;
- replacing a portion of the placeholder layers to form one or more lateral isolation structures around the vertical passage, below the etch selective layer, wherein the one or more lateral isolation structures include modified silicon oxide to lower a dielectric constant compared to silicon oxide;
- replacing a remaining portion of the placeholder layers with a first conductor material to form conductor layers;
- removing the etch selective layer to form a lateral cavity;
- and
- filling the lateral cavity and the vertical passage with a second conductor to form an electrical connection with a selected conductor layer adjacent to the lateral cavity.
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Dependencies are inferred from the claim text.