US 2026/0040532 A1 · SEMICONDUCTOR MEMORY DEVICE

Abstract

A semiconductor memory device may include a bit line extending lengthwise in a first horizontal direction on a first plane; a channel structure on a second plane apart from the first plane in a vertical direction, the channel structure being shifted from the bit line in a second horizontal direction in a plan view and not overlapping the bit line in the vertical direction, and the second horizontal direction being orthogonal to the first horizontal direction; an insulating structure between the bit line and the channel structure, the insulating structure filling a space between the first plane and the second plane; and a contact plug passing through the insulating structure in the vertical direction. A bottom surface of the contact plug may be in contact with an upper surface of the bit line. An upper sidewall of the contact plug may be in contact with the channel structure.

Claims20

Dependent claims

A semiconductor memory device comprising:

a bit line extending lengthwise in a first horizontal direction on a first plane;
a channel structure on a second plane that is apart from the first plane in a vertical direction, the channel structure being shifted from the bit line in a second horizontal direction in a plan view and not overlapping the bit line in the vertical direction, and the second horizontal direction being orthogonal to the first horizontal direction;
an insulating structure between the bit line and the channel structure, the insulating structure filling a space between the first plane and the second plane;
and
a contact plug passing through the insulating structure in the vertical direction, a bottom surface of the contact plug being in contact with an upper surface of the bit line, and an upper sidewall of the contact plug being in contact with the channel structure.

2 more elements

A semiconductor memory device comprising:

a base insulating film;
and
a memory cell array including a plurality of memory cells repeatedly arranged on the base insulating film in a first horizontal direction and a second horizontal direction that are orthogonal to each other,
wherein the memory cell array includes
a plurality of bit lines in the base insulating film and each extending lengthwise in the first horizontal direction on a first plane on the base insulating film, the plurality of bit lines being apart from each other in the second horizontal direction,
a plurality of channel structures repeatedly arranged in the first horizontal direction and the second horizontal direction on a second plane that is apart from the first plane on the base insulating film in a vertical direction,
an insulating structure between the plurality of bit lines and the plurality of channel structures, the insulating structure filling a space between the first plane and the second plane, and
a plurality of contact plugs passing through the insulating structure in the vertical direction,
wherein a bottom surface of each of the plurality of contact plugs is in contact with an upper surface of an underlying bit line among the plurality of bit lines, and an upper sidewall of each of the plurality of contact plugs is in contact with an adjacent one of the plurality of channel structures, and
wherein each of the plurality of channel structures is shifted in the second horizontal direction from an adjacent one of the plurality of bit lines and does not to overlap the adjacent one of the plurality of bit lines in the vertical direction.

7 more elements

A semiconductor memory device comprising:

a base insulating film;
a bit line extending lengthwise in a first horizontal direction on a first plane on the base insulating film;
a channel structure including a horizontal channel portion and a pair of vertical channel portions integrally connected to the horizontal channel portion, the horizontal channel portion having a nonlinear recess sidewall and extending along a second plane that is apart from the first plane in a vertical direction, and the pair of vertical channel portions respectively extending from both ends of the horizontal channel portion in a direction away from the horizontal channel portion in the vertical direction, the both ends of the horizontal channel portion being based on the first horizontal direction;
an insulating structure between the bit line and the channel structure and filling a space between the first plane and the second plane;
a contact plug passing through the insulating structure in the vertical direction, a bottom surface of the contact plug being in contact with an upper surface of the bit line, and an upper sidewall of the contact plug being in contact with the nonlinear recess sidewall of the horizontal channel portion;
a pair of word lines over the channel structure and respectively facing the pair of vertical channel portions in the first horizontal direction;
and
a pair of gate dielectric films between the channel structure and the pair of word lines,
wherein each of the channel structure, the pair of word lines, and the pair of gate dielectric films are shifted from the bit line in a second horizontal direction in a plan view and do not overlap the bit line in the vertical direction, and the second horizontal direction crosses the first horizontal direction.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20