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US 2026/0040530 A1Published application
Semiconductor device with independent source-drain region profiles for low voltage and high voltage finfet transistors
AssigneeMicron Technology, Inc.
InventorsTakehiro HIRAMATSU, Toshihiko MIYASHITA
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Abstract
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a first transistor structure for a first integrated circuit device. The first transistor structure includes a first source-drain region having a truncated elliptical shape. The integrated assembly includes a second transistor structure for a second integrated circuit device. The second transistor includes a second source-drain region having an approximately semi-elliptical shape.
Claims20
An integrated assembly, comprising:
- a first transistor structure for a first integrated circuit device, comprising:
- a first spacer along a first sidewall of a first gate structure;
- a second spacer along a second sidewall of a second gate structure;
- a first source-drain region having a truncated elliptical shape that is between the first spacer and the second spacer and that penetrates into a first fin below the first spacer and the second spacer;
- and
- a second transistor structure for a second integrated circuit device, comprising:
- a third spacer along a third sidewall of a third gate structure;
- a fourth spacer along a fourth sidewall of a fourth gate structure;
- and
- a second source-drain region having an approximately semi-elliptical shape that is between the third spacer and the fourth spacer and that penetrates into a second fin below the third spacer and the fourth spacer.
7 more elements
An apparatus, comprising:
- a first integrated circuit device, comprising;
- a first fin field effect transistor structure, comprising:
- a first gate structure having an outer edge defining a first approximately linear boundary;
- and
- a first source-drain region, comprising:
- a first surface region located a first distance from the first approximately linear boundary;
- and
- a first mid-region located a second distance from the first approximately linear boundary,
- wherein the second distance is less than the first distance;
- and
- a first tip region located a third distance from the first approximately linear boundary,
- wherein the third distance is greater than or equal to the first distance;
- and
- a second integrated circuit device, comprising:
- a second fin field effect transistor structure, comprising:
- a second gate structure having a second outer edge defining a second approximately linear boundary;
- and
- a second source-drain region, comprising:
- a second surface region located a fourth distance from the second approximately linear boundary;
- and
- a second mid-region located a fifth distance from the second approximately linear boundary,
- wherein the fifth distance is greater less than fourth distance;
- and
- a second tip region located a sixth distance from the second approximately linear boundary,
- wherein the sixth distance is greater than the fifth distance.
22 more elements
A method, comprising:
- forming a first dummy gate over a first fin and a second dummy gate over a second fin;
- forming a first spacer along a first sidewall of the first dummy gate and a second spacer along a second sidewall of the second dummy gate;
- forming a first cavity that penetrates into the first fin and that has a first profile,
- wherein a contour of the first profile underlaps the first spacer;
- forming a second cavity that has a second profile that is different than the first profile and that penetrates into the second fin,
- wherein a contour of the second profile remains clear of underlapping the second spacer;
- and
- forming a first multi-layer source-drain region in the first cavity and a second multi-layer source-drain region in the second cavity.
5 more elements
Dependencies are inferred from the claim text.