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US 2026/0039282 A1Published application
Phase and duty cycle trim for multi-phase clocking
AssigneeMicron Technology, Inc.
InventorsTyler J. Gomm, Yasuo Satoh
Life of this patent
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Abstract
Systems and methods are provided for generating timing control signals for phase and duty cycle trimming to reduce or eliminate a quadrature error of a clock signal in a memory device. The memory device employs a trim circuit to perform phase tuning to reduce or eliminate the quadrature error. Different phase tuning settings are used by the trim circuit for different types of quadrature errors. The trim circuit adjusts different phases of the clock signal independently or dependently based on the phase tuning settings.
Claims20
A trim circuit, comprising:
- a control circuit configured to:
- receive a select signal to select a type of phase tuning for a plurality of phase clock signals of a clock signal;
- and
- generate a plurality of phase adjustment signals for the plurality of phase clock signals of the clock signal based on the select signal;
- and
- a duty cycle adjuster (DCA) configured to:
- receive the plurality of phase adjustment signals from the control circuit;
- and
- use the plurality of phase adjustment signals to adjust the plurality of phase clock signals.
6 more elements
A method, comprising:
- determining a phase tuning setting to correct a quadrature error of a clock signal;
- generating a select signal corresponding to the phase tuning setting;
- and
- generating a plurality of phase adjustments signals by using the select signal.
1 more element
An apparatus, comprising:
- a 4-phase clock divider configured to divide a clock signal into four divided clock signals having respective phases:
- and
- a trim circuit configured to adjust the four divided clock signals using respective phase adjustments generated for the four divided clock signals based on an error of the clock signal.
Dependencies are inferred from the claim text.