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US 2026/0039280 A1Published application
Memory devices with reduced timing variation and methods for operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPerng-Fei Yuh, Tomohiko Yano
Life of this patent
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Abstract
A circuit includes a current source configured to provide a reference current and a plurality of transistors each configured to receive the reference current from the current source. Each of the plurality of transistors has a same conductive type and includes a first source/drain terminal connected to a gate terminal of a first neighboring one of the transistors, a second source/drain terminal connected to ground, and a gate terminal connected to a source/drain terminal of a second neighboring one of the transistors.
Claims20
A circuit, comprising:
- a current source configured to provide a reference current;
- a plurality of transistors each configured to receive the reference current from the current source, wherein each of the plurality of transistors has a same conductive type and includes:
- a first source/drain terminal connected to a gate terminal of a first neighboring one of the plurality of transistors;
- a second source/drain terminal connected to ground;
- and
- a gate terminal connected to a source/drain terminal of a second neighboring one of the plurality of transistors.
3 more elements
A circuit, comprising:
- a current source configured to provide a reference current;
- a plurality of transistors each configured to receive the reference current from the current source, wherein each of the plurality of transistors has a same conductive type, and the reference current is proportional to a threshold voltage of the plurality of transistors, the plurality of transistors including:
- a first transistor configured to provide a first signal;
- and
- a second transistor configured to provide a second signal being a delayed version of the first signal, wherein the second signal falls in response to the first signal rising to the threshold voltage.
2 more elements
A method, comprising:
- providing a reference current to a plurality of transistors having a same conductive type, wherein the reference current is proportional to a threshold voltage of the plurality of transistors;
- and
- in response to receiving the reference current, providing, by the plurality of transistors, a plurality of signals, each of which is a delayed version of each other, wherein when a first one of the plurality of signals rises to the threshold voltage, a second signal falls.
Dependencies are inferred from the claim text.