Cross temperature nand read adjustment
AssigneeSanDisk Technologies LLC
InventorsAlbert Bor Kai Chen, Sujjatul Islam, Jiahui Yuan
Life of this patent
Estimating the term…
Abstract
Technology for re-calibrating a temperature coefficient (Tco) for reading NAND memory cells. The Tco may be re-calibrated based on an amount of data retention impact to NAND memory cells since the NAND memory cells were programmed. The data retention impact may be measured by determining a shift to a candidate Vt distribution. The candidate Vt distribution may be selected as one that exhibits a significant data retention impact. The Tco may include, but is not limited to a bit line voltage Tco or a Vread Tco. The bit line voltage Tco may be used to establish the bit line voltage during read. The Vread Tco may be used to establish a voltage to unselected word lines during read.
Claims20
An apparatus comprising:
- one or more control circuits configured to connect to a NAND memory structure, the NAND memory structure having blocks having NAND strings and word lines associated with the NAND strings, the NAND memory structure having bit lines associated with the NAND strings, the one or more control circuits configured to:
- measure a data retention impact to a data state of a group of NAND memory cells in a selected block of NAND memory cells since the group was programmed to the data state;
- set a temperature coefficient (Tco) based on the data retention impact;
- and
- read NAND memory cells in the selected block based on the set Tco.
A method for operating non-volatile storage, the method comprising:
- determining a bit line voltage temperature coefficient (Tco) based on a shift to a threshold voltage distribution to which a group of NAND memory cells in the non-volatile storage were programmed, the NAND memory cells associated with a set of bit lines in the non-volatile storage;
- applying a bit line voltage to the set of bit lines that has a magnitude based on the bit line Tco;
- and
- reading selected NAND memory cells associated with the set of bit lines while applying the bit line voltage to the set of bit lines.
A non-volatile memory system, comprising:
- a NAND memory structure having NAND memory cells, bit lines associated with the NAND memory cells and word lines associated with the NAND memory cells;
- and
- one or more control circuits in communication with the NAND memory structure, the one or more control circuits configured to:
- determine a number of first NAND memory cells in a selected block having a threshold voltage within a voltage range in a lower tail of a candidate threshold voltage distribution;
- determine a bit line voltage temperature coefficient (Tco) based on the number of first NAND memory cells having a threshold voltage within the voltage range;
- apply a voltage to the bit lines that is based on the bit line voltage Tco;
- and
- read second NAND memory cells in the selected block while applying the voltage that is based on the bit line voltage Tco to the bit lines.
Dependencies are inferred from the claim text.