Memory device and memory system
AssigneeSK hynix Inc.
InventorsDong Hee HAN, Seong Yoon KANG, Mun Seon JANG, Sang Uhn CHA
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Abstract
A memory device includes a memory cell array including a plurality of cell blocks, each cell block including a plurality of memory cells and sharing sub-word line drivers with adjacent cell blocks; a data input/output circuit configured to input and output data corresponding to the plurality of cell blocks through a plurality of data pads; and a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting, according to an output control signal, a number of bits of data output from cell blocks sharing activated sub-word line drivers.
Claims20
A memory device comprising:
- a memory cell array including a plurality of cell blocks, each cell block including a plurality of memory cells and sharing sub-word line drivers with adjacent cell blocks;
- a data input/output circuit configured to input and output data corresponding to the plurality of cell blocks through a plurality of data pads;
- and
- a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting, according to an output control signal, a number of bits of data output from cell blocks sharing activated sub-word line drivers.
A memory device comprising:
- a memory cell array including a plurality of cell groups, each group including two adjacent cell blocks among a plurality of cell blocks and sharing sub-word line drivers with adjacent cell groups;
- a data input/output circuit configured to input and output data corresponding to the plurality of cell blocks through a plurality of data pads;
- and
- a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting a number of bits of data output from cell groups sharing activated sub-word line drivers.
A memory system comprising:
- a memory module including a plurality of memory devices;
- and
- a memory controller configured to provide a command and an address to control the memory module, and output and receive data to and from the memory module,
- wherein at least one of the plurality of memory devices includes:
- a memory cell array including a plurality of cell blocks, each block including a plurality of memory cells and sharing sub-word line drivers with adjacent cell blocks;
- a data input/output circuit configured to input and output the data of the plurality of cell blocks through a plurality of data pads;
- and
- a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting, according to an output control signal, a number of bits of data output from cell blocks sharing activated sub-word line drivers.
Dependencies are inferred from the claim text.