Capacitive sensing with a micropump in a memory device

A memory device comprising:

• an array of memory cells comprising at least a first string and a second string;
• a bitline, coupled with sensing circuitry, configured to provide a first read current to the first string and a second read current to the second string;
• a first micropump coupled between the bitline and a first sense transistor, the first sense transistor having a first gate terminal coupled with the first string;
• a second micropump coupled between the bitline and a second sense transistor, the second sense transistor having a second gate terminal coupled with the second string;
• and
• control logic coupled to the first micropump and the second micropump, the control logic to concurrently activate the first micropump and the second micropump such that the first read current matches the second read current.

A memory device comprising:

• a sense transistor having a gate terminal coupled with a local bitline;
• data read path circuitry positioned at least between the sense transistor and a global bitline, wherein the global bitline is coupled with a page buffer;
• a micropump that is integrated within the data read path circuitry;
• and
• control logic coupled with the data read path circuitry, the page buffer, and the global bitline, the control logic to perform operations comprising:
• activating a write enable signal and a bitline clamp signal to pre-charge the global bitline;
• after a pre-charge period, causing a voltage of a selected wordline to ramp up, the selected wordline being associated with a memory cell that is selectively coupled to the local bitline and to be read by the page buffer;
• deactivating the bitline clamp signal after a clamping period;
• and
• activating, in response to detecting the sense transistor being turned on, the micropump to cause a constant read current to flow between the global bitline and the sense transistor.