Dummy word line positioning for a plug for protection of backside source formation of vertical planar memory cells

A method at a memory system, comprising:

• receiving a request to access one or more memory cells of a plurality of memory cells of the memory system, wherein the one or more memory cells are positioned in a first layer of a plurality of layers of memory cell pillars within the memory system;
• applying, based at least in part on the request, a first voltage to a first word line of a plurality of word lines of the memory system, the first word line positioned within the first layer of the memory system;
• activating, based at least in part on the request, one or more bit line structures of the memory system using a selector and one or more voltage lines, wherein the one or more bit line structures extend in a first direction through a first subset of layers of the plurality of layers, the first subset of layers comprising at least the first layer, wherein activating the one or more bit line structures comprises:
• applying a second voltage to the selector of the memory system, wherein the selector is coupled with a plug of conductive material that extends, in a first direction, through a second subset of layers of the plurality of layers, the second subset of layers positioned below the plurality of memory cells and the first subset of layers relative to a substrate of the memory system, the plug in contact with the one or more bit line structures;
• and
• applying one or more third voltages to the one or more voltage lines of the memory system, wherein the one or more voltage lines are coupled with the plug within the second subset of layers of the plurality of layers, and wherein a magnitude of the one or more third voltages is based at least in part on the second voltage;
• and
• accessing the one or more memory cells based at least in part on applying the first voltage to the first word line and activating the one or more bit line structures.

A memory system, comprising:

• one or more memory devices;
• and
• processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
• receive a request to access one or more memory cells of a plurality of memory cells of the memory system, wherein the one or more memory cells are positioned in a first layer of a plurality of layers of memory cell pillars within the memory system;
• apply, based at least in part on the request, a first voltage to a first word line of a plurality of word lines of the memory system, the first word line positioned within the first layer of the memory system;
• activate, based at least in part on the request, one or more bit line structures of the memory system using a selector and one or more voltage lines, wherein the one or more bit line structures extend in a first direction through a first subset of layers of the plurality of layers, the first subset of layers comprising at least the first layer, wherein, to activate the one or more bit line structures, the processing circuitry is configured to:
• apply a second voltage to the selector of the memory system, wherein the selector is coupled with a plug of conductive material that extends, in a first direction, through a second subset of layers of the plurality of layers, the second subset of layers positioned below the plurality of memory cells and the first subset of layers relative to a substrate of the memory system, the plug in contact with the one or more bit line structures;
• and
• apply one or more third voltages to the one or more voltage lines of the memory system, wherein the one or more voltage lines are coupled with the plug within the second subset of layers of the plurality of layers, and wherein a magnitude of the one or more third voltages is based at least in part on the second voltage;
• and
• access the one or more memory cells based at least in part on applying the first voltage to the first word line and activating the one or more bit line structures.