Memory device and method of manufacturing the memory device

A memory device, comprising:

• a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers that are alternately stacked in a cell array area and a contact area, the cell array area including first, second, third, and fourth cell areas;
• a plurality of cell plugs formed within the stacked structure in the cell array area;
• a plurality of select line contacts coupled to the conductive layer that is allocated as a select line among the plurality of conductive layers;
• a first separation pattern disposed between the first cell area and the second cell area, and penetrating the conductive layer that is allocated as the select line in the cell array area, the first separation pattern extending from the cell array area to the contact area;
• a second separation pattern disposed between the second cell area and the third cell area, and penetrating the conductive layer that is allocated as the select line in the cell array area, the second separation pattern extending from the cell array area to the contact area;
• and
• a third separation pattern disposed between the third cell area and the fourth cell area, and penetrating the conductive layer that is allocated as the select line in the cell array area, the third separation pattern extending from the cell array area to the contact area,
• wherein the first separation pattern and the third separation pattern separate the plurality of select line contacts from each other.

A method of manufacturing a memory device, comprising:

• forming a stacked structure by alternately stacking a plurality of conductive layers and a plurality of interlayer insulating layers in a cell array area and a contact area;
• forming a plurality of cell plugs in the stacked structure in the cell array area;
• forming a pre-select line contact coupled to the conductive layer that is allocated as a select line among the plurality of conductive layers;
• forming a trench that penetrates the conductive layer that is allocated as the select line, the trench extending from the cell array area to the contact area;
• and
• filling the trench with an insulating layer to form a separation pattern,
• wherein the trench penetrates the pre-select line contact to separate the pre-select line contact into a plurality of select line contacts.

A method of manufacturing a memory device, comprising:

• forming a stacked structure by alternately stacking a plurality of conductive layers and a plurality of interlayer insulating layers in a cell array area and a contact area, the cell array area including a first cell area and a second cell area;
• forming a plurality of cell plugs within the stacked structure in the cell array area;
• forming a first select line contact and a second select line contact coupled to the conductive layer that is allocated as a select line among the plurality of conductive layers;
• forming a trench that penetrates the conductive layer that is allocated as the select line between the first cell area and the second cell area, the trench extending from the cell array area to the contact area;
• and
• filling the trench with an insulating layer to form a separation pattern,
• wherein the trench separates the first select line contact and the second select line contact from each other.