Coordinating processing tasks between one-dimensional processing engines and two-dimensional processing engines

A system, comprising:

• one or more processors to:
• receive a first signal from a vector processing unit (VPU) to process intermediate results of a vision processing task, the intermediate results located in a first output buffer of a vector memory (VMEM) accessed by the VPU;
• retrieve the data from the output buffer of the VMEM;
• provide, based at least on the intermediate results, results of the vision processing task in a second output buffer in the VMEM;
• and
• transmit a second signal to the VPU indicating that the intermediate results have been processed.

A system on a chip, comprising:

• a memory;
• a two-dimensional vector processor;
• and
• a one-dimensional vector processor, wherein the one-dimensional vector processor executes instructions to:
• retrieve, from the memory, input data for a vision processing task;
• provide, based at least on the input data, intermediate results of the vision processing task in an output buffer in the memory;
• transmit a first signal to the two-dimensional vector processor to begin processing the intermediate results in the output buffer;
• receive, from the two-dimensional vector processor, a second signal that the two-dimensional vector processor has completed processing of the intermediate results.