Weight-stationary matrix multiply accelerator with tightly coupled l2 cache

A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing an accelerator, wherein the accelerator includes a weight-stationary systolic array of one or more multiply-accumulate units, wherein the accelerator is coupled to a memory hierarchy, and wherein the memory hierarchy is coupled to a processor core;
• sending, by the processor core, a work request to the accelerator, wherein the work request is based on execution of a machine learning model and an activation matrix;
• loading, by the accelerator, a weight matrix and the activation matrix, wherein the loading is responsive to the work request and wherein the loading uses the memory hierarchy;
• multiplying, by the accelerator, the weight matrix by the activation matrix, wherein the multiplying results in an answer matrix;
• storing, by the accelerator, the answer matrix in the memory hierarchy;
• and
• obtaining, by the processor core, from the memory hierarchy, the answer matrix that was stored.

A computer system for instruction execution comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access an accelerator, wherein the accelerator includes a weight-stationary systolic array of one or more multiply-accumulate units, wherein the accelerator is coupled to a memory hierarchy, and wherein the memory hierarchy is coupled to a processor core;
• send, by the processor core, a work request to the accelerator, wherein the work request is based on execution of a machine learning model and an activation matrix;
• load, by the accelerator, a weight matrix and the activation matrix, wherein the loading is responsive to the work request and wherein the loading uses the memory hierarchy;
• multiply, by the accelerator, the weight matrix by the activation matrix, wherein the multiplying results in an answer matrix;
• store, by the accelerator, the answer matrix in the memory hierarchy;
• and
• obtain, by the processor core, from the memory hierarchy, the answer matrix that was stored.