Variable-Bitwidth Matrix Multiplication
AssigneeDeepMind Technologies Limited
InventorHerman Henry Schmit
Life of this patent
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Abstract
Systems and methods for performing variable-bitwidth matrix multiplication are provided. For example, a processor device can include dot product hardware configured to perform a plurality of dot products at a first bitwidth to generate a plurality of first-bitwidth dot product outputs. The processor device can include programmable adder hardware. The programmable adder hardware can be configured to obtain data indicative of one or more target bitwidths. The programmable adder hardware can be configured to combine, based on the data indicative of the one or more target bitwidths, one or more subsets of the plurality of first-bitwidth dot product outputs according to the one or more target bitwidths.
Claims20
A processor device for performing variable-bitwidth matrix multiplication, comprising:
- dot product hardware configured to perform a plurality of dot products at a first bitwidth to generate a plurality of first-bitwidth dot product outputs;
- and
- programmable adder hardware configured to:
- obtain data indicative of one or more target bitwidths;
- and
- combine, based on the data indicative of the one or more target bitwidths, one or more subsets of the plurality of first-bitwidth dot product outputs according to the one or more target bitwidths.
A method, comprising:
- performing, by one or more processor devices, a plurality of dot products at a first bitwidth to generate a plurality of first-bitwidth dot product outputs;
- obtaining, by the one or more processor devices, data indicative of one or more target bitwidths;
- and
- combining, by the one or more processor devices based on the data indicative of the one or more target bitwidths, one or more subsets of the plurality of first-bitwidth dot product outputs according to the one or more target bitwidths.
A computing system, comprising:
- one or more processor devices for performing variable-bitwidth matrix multiplication, the one or more processor devices comprising:
- dot product hardware configured to perform a plurality of dot products at a first bitwidth to generate a plurality of first-bitwidth dot product outputs;
- and
- programmable adder hardware configured to:
- obtain data indicative of one or more target bitwidths;
- and
- combine, based on the data indicative of the one or more target bitwidths, one or more subsets of the plurality of first-bitwidth dot product outputs according to the one or more target bitwidths.
Dependencies are inferred from the claim text.