Compute-near-memory-system event hardware performing a reduction operation
AssigneeMicron Technology, Inc.
InventorsPatrick Estep, Randall Meyer, Tony M. Brewer, Michael Keith Dugan
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Abstract
System and techniques for performing a reduction operation using event hardware are described herein. In an environment in which sub-processes are run on different processors, and these sub-processes inform a head process via event messaging, when a reduction operation is completed by a sub-process of the sub-processes, the partial result of the sub-process is received at event management circuitry of the processor of the head process. The event management circuitry uses the partial result to update an incremental result to the reduction operation as each sub-process result event message is received.
Claims20
An apparatus for reduction operation performance by event hardware, the apparatus comprising:
- an interface configured to communicate with a second processor;
- and
- processing circuitry that includes:
- a processor configured to:
- execute an instruction to perform a reduction operation on data;
- communicate, to the second processor using the interface, a subset of the data and the reduction operation;
- and
- write a count and the reduction operation to event management circuitry of the apparatus;
- and
- the event management circuitry, which is configured to:
- receive an event from the second processor, the event including a result, the result created by the reduction operation by the second processor on the subset of the data;
- decrement the count in response to receipt of the event;
- and
- apply the reduction operation to the result and a current state of a whole of the reduction operation to produce a new state of the whole of the reduction operation, wherein the apparatus is a processor or accelerator in a near-memory-compute-system, wherein the event management circuitry is also configured to send or receive thread-level messages between threads running on the processing circuitry and other threads running on other processors or accelerators in the near-memory-compute-system including the second processor.
A non-transitory machine readable medium including instructions for reduction operation performance by event hardware, the instructions, when executed by processing circuitry, causing the processing circuitry to perform operations comprising:
- executing, on a first processor, an instruction to perform a reduction operation on data;
- communicating, using an interface of the first processor, a subset of the data and the reduction operation to a second processor;
- writing the reduction operation and a count to event management circuitry of the first processor;
- receiving, by the event management circuitry via the interface, an event from the second processor, the event including identification that it is an event and a result, the result created by performance of the reduction operation by the second processor on the subset of the data;
- decrementing, by the event management circuitry, the count in response to receipt of the event;
- and
- applying, by the event management circuitry, the reduction operation to the result and a current state of a whole of the reduction operation to produce a new state of the whole of the reduction operation, wherein the first processor and the second processor are in a near-memory-compute-system, wherein the event management circuitry is also configured to send or receive thread-level messages between threads running on the first processor and other threads running on other processors or accelerators in the near-memory-compute-system including the second processor.
Dependencies are inferred from the claim text.