System and method for memory bandwidth reduction using a programmable cache line

A non-transitory computer-readable medium storing a set of instructions for memory bandwidth reduction using a programmable cache line, the set of instructions comprising:

• one or more instructions that, when executed by one or more processors of a device, cause the device to:
• generate an instruction to render a modified texture based on a preexisting texture, the preexisting texture stored as a plurality of lines in a memory;
• select an amount of data to read from a first line of a texture based on the modification;
• configure a programmable cache line to read into a cache at least the selected amount of data from a unique address of the memory corresponding to the first line;
• and
• store at least a portion of the selected amount of data in a first line of a framebuffer.

A system for memory bandwidth reduction using a programmable cache line comprising:

• a processing circuitry;
• a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
• generate an instruction to render a modified texture based on a preexisting texture, the preexisting texture stored as a plurality of lines in a memory;
• select an amount of data to read from a first line of a texture based on the modification;
• configure a programmable cache line to read into a cache at least the selected amount of data from a unique address of the memory corresponding to the first line;
• and
• store at least a portion of the selected amount of data in a first line of a framebuffer.