Computer architecture to validate image frame and image line data in a single pass
AssigneeNVIDIA Corporation
InventorsLachlan Francis DOWLING, Dawid Stanislaw PAJAK, Ching-Yu HUNG
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Abstract
Aspects of this technical solution can increase processing speed in low-latency application areas, while maintaining integrity of error correction detection at those higher speeds. For example, in image-processing environments associated with autonomous navigation (e.g., driving), a large volume of image data is to be rapidly and accurately processed to maintain reliable and up-to-date models of a physical environment. Thus, embodiments in accordance with this disclosure can provide high-speed and accurate error correction of input frame data beyond the capability of CPU processing or general GPU processing to achieve.
Claims20
A system, comprising:
- one or more processors to:
- obtain a plurality of encodings in parallel via respective lanes of a processor, each of the plurality of encodings corresponding to respective rows of a frame of data;
- append, in parallel via the respective lanes of the processor, a first set of bits to each of a set of rows of the respective rows;
- load, in parallel via the respective lanes of the processor, respective encodings of the plurality of encodings into corresponding rows of the set of rows;
- append, in parallel via the respective lanes of the processor, a plurality of sets of bits to the set of rows;
- shift one or more of the set of rows to align each of the encodings with at least one of the first set of bits or one or more of the plurality of sets of bits;
- and
- load, in parallel via the respective lanes of the processor, each row of the set of rows including the encodings into a common row to form a frame encoding corresponding to the frame of the data.
A system-on-a-chip (SoC), comprising:
- at least one graphics processing unit (GPU) providing multi-core parallel processing via a plurality of respective lanes, the GPU to:
- determine, in parallel via a processor, a first set of bits for each row of a set of respective rows of a frame of data;
- load, in parallel via the processor, respective encodings of the plurality of encodings into corresponding rows of the set of rows;
- determine, in parallel via the processor, a plurality of sets of bits for the set of rows;
- combine each of the encodings with at least one of the first set of bits or one or more of the plurality of sets of bits;
- and
- load, in parallel via the processor, each of the set of rows including the encodings into a common row to form a frame encoding corresponding to the frame of the data.
A method, comprising:
- obtaining a plurality of encodings in parallel via respective lanes of a processor, each of the plurality of encodings corresponding to respective rows of a frame of data;
- appending, in parallel via the respective lanes of the processor, a first set of bits to each of a set of rows of the respective rows;
- loading, in parallel via the respective lanes of the processor, respective encodings of the plurality of encodings into corresponding rows of the set of rows;
- appending, in parallel via the respective lanes of the processor, a plurality of sets of bits to the set of rows;
- shifting one or more of the set of rows to align each of the encodings with at least one of the first set of bits or one or more of the plurality of sets of bits;
- and
- loading, in parallel via the respective lanes of the processor, each of the set of rows including the encodings into a common row to form a frame encoding corresponding to the frame of the data.
Dependencies are inferred from the claim text.