Corrective reads implementing incremental reads with respect to adjacent wordlines

A memory device comprising:

• a memory array;
• and
• control logic, operatively coupled with the memory array, to perform operations comprising:
• maintaining, at a first primary data cache, a first bit of a first read result of a first read at a first primary data cache, a second bit of the first read result at a secondary data cache, and a second read result of a second read at a second primary data cache, wherein the first read is performed with respect to a first cell of the memory array, and wherein the second read is performed with respect to a second cell of the memory array;
• and
• causing a third read to be performed with respect to a target cell of the memory array, wherein the target cell is adjacent to the first cell and the second cell.

A memory device comprising:

• a memory array;
• and
• control logic, operatively coupled with the memory array, to perform operations comprising:
• maintaining, at a first primary data cache, a first bit of a first read result of a first read at a first primary data cache, a second bit of the first read result at a secondary data cache, and a second read result of a second read at a second primary data cache, wherein:
• the first read is performed with respect to a first cell of the memory array;
• the second read is performed with respect to a second cell of the memory array;
• the first read result is a 2-bit read result;
• and
• the second read result is a 1-bit read result;
• causing a third read to be performed with respect to a target cell of the memory array, wherein the target cell is adjacent to the first cell and the second cell;
• and
• storing, to a third primary data cache, a third read result of the third read using a third primary data cache.