Three-dimensional ferroelectric tunnel junction device for multiply-accumulate operations
AssigneeMicron Technology, Inc.
InventorsKamal Karda, Hernan Castro
Life of this patent
Estimating the term…
Abstract
Systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. In one approach, a memory cell array has memory cells arranged vertically above a semiconductor substrate. Each memory cell stores a weight using a ferroelectric tunnel junction (FTJ) device as a storage element. Local digit lines connect to terminals of the memory cells. The local digit lines extend vertically above the substrate. Select transistors connect to the local digit lines. Select lines control the select transistors, and are used to encode an input pattern to multiply by the stored weights. Accumulation circuitry sums output currents from the memory cells.
Claims21
An apparatus comprising:
- a ferroelectric layer between a first electrode and a second electrode;
- and
- an undoped semiconductor layer in contact with the ferroelectric layer.
An apparatus comprising:
- a semiconductor substrate;
- a plurality of memory cells stacked vertically above the semiconductor substrate, each memory cell comprising a select transistor and a ferroelectric tunnel junction (FTJ) device;
- and
- wordlines configured to apply gate voltages to the select transistors.
A method comprising:
- forming a plurality of transistors, each transistor comprising a silicon layer;
- forming an opening in electrical isolation, the opening exposing an end of the silicon layer of each transistor;
- and
- forming a ferroelectric layer at the end of the silicon layer for each transistor.
Dependencies are inferred from the claim text.