Semiconductor device

A semiconductor device comprising:

• a substrate including an active pattern;
• a lower power line buried in a lower portion of the substrate;
• a channel pattern on the active pattern and including a plurality of semiconductor patterns, the plurality of semiconductor patterns being spaced apart from each other and stacked, and including a lowermost first semiconductor pattern;
• a gate electrode crossing the active pattern, and including a first inner gate electrode interposed between the active pattern and the lowermost first semiconductor pattern;
• a source/drain pattern connected to the channel pattern;
• a rear surface active contact electrically connecting the lower power line and the source/drain pattern;
• and
• a rear surface filler structure disposed under the first inner gate electrode,
• wherein the rear surface filler structure includes:
• a lower filler portion;
• and
• an upper filler portion on the lower filler portion, and
• wherein a slope of a sidewall of the upper filler portion is different from or the same as a slope of a sidewall of the lower filler portion.

A semiconductor device comprising:

• a substrate including an active pattern;
• an element isolation film provided on the substrate to define the active pattern;
• a channel pattern on the active pattern and including a plurality of semiconductor patterns, the plurality of semiconductor patterns being spaced apart from each other and stacked, and including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern;
• source/drain patterns connected to the channel pattern, and including a first source/drain pattern and a second source/drain pattern horizontally spaced apart from each other;
• a gate electrode between the plurality of semiconductor patterns, and including a first inner electrode, a second inner electrode, and a third inner electrode interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns, and an outer electrode on the third semiconductor pattern;
• a gate insulating film interposed between the gate electrode and the channel pattern;
• gate spacers on sidewalls of the gate electrode;
• a gate capping pattern on an upper surface of the gate electrode;
• an interlayer insulating layer covering the source/drain pattern and the gate capping pattern;
• an upper active contact penetrating the interlayer insulating layer to be electrically connected to the first source/drain pattern;
• a metal-semiconductor compound layer interposed between the upper active contact and the first source/drain pattern;
• a gate contact penetrating the interlayer insulating layer and the gate capping pattern to be electrically connected to the gate electrode;
• a first metal layer on the interlayer insulating layer and including a first line electrically connected to the gate contact;
• a second metal layer on the first metal layer and including a second line electrically connected to the first metal layer;
• a lower power line provided under the substrate;
• a rear surface active contact penetrating the substrate to electrically connect the lower power line and the second source/drain pattern;
• and
• a rear surface filler structure penetrating the substrate to be disposed under the gate insulating film on the first inner electrode,
• wherein the rear surface filler structure includes:
• a first filler pattern adjacent to the gate insulating film;
• and
• a second filler pattern provided under the first filler pattern,
• wherein a bottom surface of the first filler pattern has a first level,
• wherein a bottom surface of the second filler pattern has a second level, and
• wherein the first level is higher than the second level.