Pin arrangement structure, package substrate, and package structure

Abstract

The present disclosure relates to a pin arrangement structure, a package substrate, and a package structure, and relates to the field of package technologies. The pin arrangement structure includes a first pin array region. First pin units and second pin units in the first pin array region are sequentially arranged alternately in a first direction, and the first pin units and the second pin units are both provided with high-speed single-ended signal pins. A number of pins of the first pin units in a second direction is greater than a number of pins of the second pin units in the second direction, two adjacent second pin units are staggered in the first direction, and first reference ground pins are arranged at other pin positions of the first pin array region. Therefore, isolation is formed between the high-speed single-ended signal pins, improving isolation between signals and reducing crosstalk between the signals. At the same time, compared with existing arrangement, the arrangement reduces the number of pins and saves a region area of the pins.

Dependencies are inferred from the claim text.