Back to results
US 2026/0031928 A1Published application
Data Processing Method and Data Processing Apparatus
AssigneeHuawei Technologies Co., Ltd.
InventorsXiaoling Yang, Kechao Huang, Huixiao Ma
Life of this patent
Estimating the term…
Abstract
A data processing method includes, for a concatenated FEC-based transmission solution, interleaving alignment that is first performed before convolutional interleaving is performed on a first data stream, to determine a boundary of each bit set in the first data stream and a boundary of each bit subset in the bit set. Further, bit subsets are sent as a granularity to each storage unit in a convolutional interleaving operation. Each bit subset includes d bits, and each storage unit is configured to store d bits. The bits in each bit subset are from v symbols, and the v symbols are respectively from v first codewords. One symbol is selected from each of the v first codewords to form a bit subset.
Claims26
A method, comprising:
- obtaining m first data streams, wherein m is an integer greater than 1, wherein each of the m first data streams is based on interleaving v lanes of first codewords, wherein the first codewords are based on first forward error correction (FEC) encoding, wherein each of the m first data streams comprises a plurality of consecutive bit sets, wherein each of the plurality of consecutive bit sets comprises t bit subsets, wherein t is an integer greater than 1, wherein each of the t bit subsets comprises d bits, wherein d=v×s, wherein v is an integer greater than 1, wherein s indicates a quantity of bits comprised in each symbol in each of the first codewords, wherein s is an integer greater than or equal to 1, wherein the bits in each of the t bit subsets are from v symbols, wherein the v symbols are respectively from v first codewords, and wherein the v first codewords are respectively from the v lanes of the first codewords;
- and
- separately delaying the m first data streams based on 3 delay lines to obtain m second data streams, wherein the 3 delay lines correspond respectively to 3 delay values, wherein the 3 delay values are 0 bits, Q×d bits, and 2Q×d bits respectively, and wherein Q is a positive integer greater than or equal to 1.
A data processing apparatus, comprising:
- a processor configured to obtain m first data streams, wherein m is an integer greater than 1, wherein each of the m first data streams is based on interleaving v lanes of first codewords, wherein the first codewords are based on first forward error correction (FEC) encoding, wherein each of the m first data streams comprises a plurality of consecutive bit sets, wherein each of the plurality of consecutive bit sets comprises t bit subsets, wherein t is an integer greater than 1, wherein each of the t bit subsets comprises d bits, wherein d=v×s, wherein v is an integer greater than 1, wherein s indicates a quantity of bits comprised in each symbol in each of the first codewords, wherein s is an integer greater than or equal to 1, wherein the bits in each of the t bit subsets are from v symbols, wherein the v symbols are respectively from v first codewords, and wherein the v first codewords are respectively from the v lanes of the first codewords;
- and
- a convolutional interleaver configured to separately delay the m first data streams based on 3 delay lines to obtain m second data streams, wherein the 3 delay lines correspond respectively to 3 delay values, wherein the 3 delay values are 0 bits, Q×d bits, and 2Q×d bits respectively, and wherein Q is a positive integer greater than or equal to 1.
A chip comprising a processor configured to:
- obtain m first data streams, wherein m is an integer greater than 1, wherein each of the m first data streams is based on interleaving v lanes of first codewords wherein the first codewords are based on first forward error correction (FEC) encoding, wherein each of the m first data streams comprises a plurality of consecutive bit sets, wherein each of the plurality of consecutive bit sets comprises t bit subsets, wherein t is an integer greater than 1, wherein each of the t bit subsets comprises d bits, wherein d=v×s, wherein v is an integer greater than 1, wherein s indicates a quantity of bits comprised in each symbol in each of the first codewords, wherein s is an integer greater than or equal to 1, wherein the bits in each of the t bit subsets are from v symbols, wherein the v symbols are respectively from v first codewords, and wherein the v first codewords are respectively from the v lanes of the first codewords;
- and
- separately delay the m first data streams based on 3 delay lines to obtain m second data streams, wherein the 3 delay lines correspond respectively to 3 delay values, wherein the 3 delay values are 0 bits, Q×d bits, and 2Q×d bits respectively, and wherein Q is a positive integer greater than or equal to 1.
An optical module comprising:
- an interface;
- and
- a processor coupled to the interface and configured to:
- obtain m first data streams through the interface, wherein m is an integer greater than 1, wherein each of the m first data streams is based on interleaving v lanes of first codewords, wherein the first codewords are based on first forward error correction (FEC) encoding, wherein each of the m first data streams comprises a plurality of consecutive bit sets, wherein each of the plurality of consecutive bit sets comprises t bit subsets, wherein t is an integer greater than 1, wherein each of the t bit subsets comprises d bits, wherein d=v×s, wherein v is an integer greater than 1, wherein s indicates a quantity of bits comprised in each symbol in each of the first codewords, wherein s is an integer greater than or equal to 1, wherein the bits in each of the t bit subsets are from v symbols, wherein the v symbols are respectively from v first codewords, and wherein the v first codewords are respectively from the v lanes of the first codewords;
- and
- separately delay the m first data streams based on 3 delay lines to obtain m second data streams, wherein the 3 delay lines correspond respectively to 3 delay values, wherein the 3 delay values are 0 bits, Q×d bits, and 2Q×d bits respectively, and wherein Q is a positive integer greater than or equal to 1.
3 more elements
Dependencies are inferred from the claim text.