Link receiver circuitry for controller-memory device interfaces in data storage devices
AssigneeSanDisk Technologies LLC
InventorsASHISH SAVADIA, RAMAKRISHNAN SUBRAMANIAN, SHIV HARIT MATHUR
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Abstract
A receiver circuitry in a storage device may operate in stages. An amplifier in a first stage may receive an input and produce a high gain for all speeds with gain booster cells and a complementary input folded cascade structure. An equalizer including a resistor and a capacitor may increase the gain at high speeds in a second stage. In a third stage, a level down shifter may correct a duty cycle error resulting from shifting a signal across domain. The receiver circuitry may thus be used in different categories of storage devices with varying requirements.
Claims15
A receiver circuitry in a storage device to provide an interface between a controller and a memory device in the storage device, the receiver circuitry comprises:
- an amplifier to receive an input and produce a high gain at high and low speeds;
- an equalizer to increase gain at high speeds;
- and
- a skew balanced level down shifter to correct a duty cycle error resulting from shifting a signal across domains.
A receiver circuitry in a storage device to provide an interface between a controller and a memory device in the storage device, the receiver circuitry comprises:
- an amplifier to operate in a first stage, receive an input. and produce a high gain with a complementary input folded cascade structure;
- an equalizer to operate in a second stage, wherein the equalizer includes a resistor and a capacitor, and the equalizer increases the gain at high speeds;
- and
- a level down shifter to operate in a third stage to correct a duty cycle error resulting from shifting a signal across domains.
A method for interfacing between a controller and a memory device in a storage device using a receiver circuitry in the storage device, the method comprising:
- receiving an input and producing a high gain with gain booster cells and a complementary input folded cascade structure in a first stage;
- increasing the gain at high speeds with an equalizer in a second stage;
- and
- correcting a duty cycle error resulting from shifting a signal across domain with a level down shifter in a third stage.
Dependencies are inferred from the claim text.