Clocking a systolic array on both edges of a clock signal
AssigneeQUALCOMM Incorporated
InventorsEric Wayne MAHURIN, Jinxia BAI, Tejaswi TALLURU, Hidayatullah CHOWDARY
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Abstract
The present disclosure is directed to an apparatus that includes a systolic array having an initial systolic stage that is clocked at a first edge of a clock signal. The apparatus further includes control logic configured to clock a first subset of a plurality of additional systolic stages of the systolic array at the first edge of the clock signal. The control logic is further configured to clock a second subset of the plurality of systolic stages at a second edge of the clock signal.
Claims20
An apparatus, comprising:
- a systolic array comprising an initial systolic stage clocked at a first edge of a clock signal, the systolic array further comprising a plurality of additional systolic stages;
- and control logic configured to clock a first subset of the plurality of additional systolic stages at the first edge of the clock signal and a second subset of the plurality of additional systolic stages at a second edge of the clock signal, the second edge being different from the first edge.
A method of operating a systolic array, comprising:
- clocking a first systolic stage of the systolic array at a first edge of a first cycle of a clock signal;
- and clocking a second systolic stage of the systolic array at a second edge of a second cycle of the clock signal that follows the first cycle of the clock signal.
An apparatus, comprising:
- means for clocking a first systolic stage of a systolic array at a first edge of a first cycle of a clock signal;
- and means for clocking a second systolic stage of the systolic array at a second edge of a second cycle of the clock signal.
Dependencies are inferred from the claim text.