Controllers in data processing engine columns
AssigneeXilinx, Inc.
InventorsJuan J. NOGUERA SERRA, David Patrick CLARKE, Javier CABEZAS RODRIGUEZ, Mikhail ASIATICI, Patrick SCHLANGEN
Life of this patent
Estimating the term…
Abstract
Embodiments herein describe a hardware accelerator with an array of data processing engines (DPEs) which includes a controller (e.g., a microcontroller) for multiple columns of the array. The controllers can be hardened circuitry that executes software code (or firmware) that controls the hardware accelerator. In one embodiment, the task of the controller is to control and orchestrate the functions performed by the hardware accelerator.
Claims20
A hardware accelerator array comprising:
- a plurality of data processing engine (DPE) tiles arranged in a plurality of columns;
- and
- a plurality of interface tiles, wherein each of the plurality of columns includes at least one of the plurality of interface tiles, wherein each of the plurality of interface tiles comprises a respective controller configured to control execution of multiple DPE tiles in a respective column of the plurality of columns, wherein each of the controllers comprises:
- direct memory access (DMA) circuitry configured to fetch commands, wherein the commands define a task to be performed by the plurality of DPE tiles;
- and
- first circuitry configured to convert the commands into instructions for controlling the execution of the multiple DPE tiles in the respective column.
A hardware accelerator array comprising:
- a plurality of data processing engine (DPE) tiles arranged in a plurality of columns;
- and
- a plurality of controllers arranged in the plurality of columns, the plurality of controllers configured to control execution of only DPE tiles in a same column, wherein each of the plurality of controllers comprises:
- direct memory access (DMA) circuitry configured to fetch commands, wherein the commands define a task to be performed by the plurality of DPE tiles;
- and
- a core comprising circuitry configured to convert the commands into instructions for controlling the execution of the DPE tiles in a respective column.
A method for controlling a plurality of data processing engine (DPE) tiles arranged in a plurality of columns in a hardware accelerator array, the method comprising:
- fetching, using a plurality of controllers, commands from a binary, wherein the plurality of controllers are disposed within the plurality of columns;
- converting, using the plurality of controllers, the commands into DMA and control instructions;
- transmitting the DMA and control instructions from the plurality of controllers to DMA circuitry in the hardware accelerator array to move data into the plurality of DPE tiles for processing;
- receiving, at the plurality of controllers, a completion signal from a tile in the hardware accelerator array when one of the DMA and control instructions is complete;
- and
- converting, at the plurality of controllers, additional commands from the binary into additional instructions for the tile.
(canceled)
Dependencies are inferred from the claim text.