US 2026/0030193 A1 · SEMICONDUCTOR DEVICE FOR CHANGING LINK SPEED AND LINK WIDTH OF PCIE LINK AND OPERATING METHOD THEREOF

Abstract

Provided are a semiconductor device for changing a link speed and a link width of a peripheral component interconnect express (PCIe) link and an operating method thereof. The semiconductor device includes the PCIe link including a plurality of lanes, and a controller configured to transceive a data link layer packet (DLLP) including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and determine whether to perform at least one of a link speed changing operation performed in a recovery state, or a link width changing operation performed in the L0p state, based on the number of times of transition and the maximum number of times of transition.

Claims20

Dependent claims

A semiconductor device, comprising:

a peripheral component interconnect express (PCIe) link comprising a plurality of lanes;
and
a controller configured to
perform a communication operation of transceiving of a data link layer packet (DLLP), the DLLP including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state of a PCIe through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and
determine whether to perform, based on the number of times of transition and the maximum number of times of transition, at least one of a link speed changing operation of reducing a link speed of the PCIe link in a recovery state of the PCIe, or a link width changing operation of reducing a link width of the PCIe link in the L0p state.

2 more elements

An operating method of a semiconductor device, the operating method comprising:

a link management operation of transceiving a link management data link layer packet (DLLP), the DLLP including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state of a peripheral component interconnect express (PCIe), through a PCIe link including a plurality of lanes in the L0 state;
a link speed changing operation of setting a link speed lower than a link speed of the PCIe link in a recovery state of the PCIe, based on a first number of times of transition being greater than the maximum number of times of transition;
and
a link width changing operation of setting a link width less than a link width of the PCIe link in the L0p state of the PCIe, based on a second number of times of transition being less than or equal to the maximum number of times of transition.

1 more element

A semiconductor device, comprising:

a port connected to a peripheral component interconnect express (PCIe) link, wherein
the port is configured to transceive a data link layer packet (DLLP) in an L0 state of a PCIe, and
the DLLP includes a DLLP type field indicating a link management DLLP, a link management type field indicating an error count among a plurality of types of link management of the PCIe, a speed down field indicating whether to speed down on a speed of the PCIe link, an L0p command field indicating an L0p command or an L0p response, an L0p entry count field indicating a number of times of transition from the L0 state to the L0p state of the PCIe, and an L0p entry limit field indicating a maximum number of times of transition with respect to the number of times of transition.

Dependencies are inferred from the claim text.

Semiconductor device for changing link speed and link width of pcie link and operating method thereof

Life of this patent

Semiconductor device for changing link speed and link width of pcie link and operating method thereof

Life of this patent

Abstract

Claims20