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AssigneeGOWIN Semiconductor Corporation
InventorDiwakar Chopperla
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A hybrid mode system containing an external device and a field-programmable gate array (“FPGA”) capable of providing configuration data to FPGA via a hybrid communication channel is disclosed. The system is able to identify a first communication protocol in accordance with at least a portion of address bits presented on a serial data line (“SDA”) wherein SDA is used as a connection between FPGA and the external device. The clock signals for receiving data are adjusted to a first clock frequency in accordance with the first communication protocol and clock cycles presented on a serial clock line (“SCL”). SCL is used to connection between FPGA and the external device. After transmitting the configuration data, a portion of FPGA is programmed to perform user-defined logic functions in response to the configuration data.
A method for selectively transmitting information to one of multiple programmable slave elements via a hybrid communication channel comprising:
A configurable semiconductor device able to process information, comprising:
A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of data processing, wherein the HDL design structure comprises:
Dependencies are inferred from the claim text.