US 2026/0030185 A1 · DELAYED MEMORY MANAGEMENT OPERATIONS

Abstract

Methods, systems, and devices for delayed memory management operations are described. A memory system may be configured to delay one or more aspects of a memory management operation and correspondingly adjust a rate of write operation performance. The memory system may delay updating L2P table entries until a first set of memory cells is full. During a memory management operation, the memory system may transfer a set of logical-to-physical (L2P) address updates to a second set of memory cells. In response to determining that the first set of memory cells is full, the memory system may read the second set of memory cells or the first set of memory cells to obtain the L2P updates. The memory system may be configured to update a rate of write operation performance based on the delayed memory management operations.

Claims22

Dependent claims

A memory system, comprising:

one or more memory devices;
and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
perform a memory management operation for a first set of one or more memory cells;
determine whether the first set of one or more memory cells is full in response to performing the memory management operation;
obtain a set of logical-to-physical address updates from a second set of one or more memory cells in response to determining that the first set of one or more memory cells is full;
and
output the set of logical-to-physical address updates to a change log in response to obtaining the set of logical-to-physical address updates from the second set of one or more memory cells.

5 more elements

A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system, cause the memory system to:

perform a memory management operation for a first set of one or more memory cells;
determine whether the first set of one or more memory cells is full in response to performing the memory management operation;
obtain a set of logical-to-physical address updates from a second set of one or more memory cells in response to determining that the first set of one or more memory cells is full;
and
output the set of logical-to-physical address updates to a change log in response to obtaining the set of logical-to-physical address updates from the second set of one or more memory cells.

2 more elements

A method, comprising:

performing a memory management operation for a first set of one or more memory cells;
determining whether the first set of one or more memory cells is full in response to performing the memory management operation;
obtaining a set of logical-to-physical address updates from a second set of one or more memory cells in response to determining that the first set of one or more memory cells is full;
and
outputting the set of logical-to-physical address updates to a change log in response to obtaining the set of logical-to-physical address updates from the second set of one or more memory cells.

2 more elements

Dependencies are inferred from the claim text.

Delayed memory management operations

Life of this patent

Delayed memory management operations

Life of this patent

Abstract

Claims22