Internal memory error correction code information for memory systems

A method, comprising:

• retrieving, by a memory system controller via a first access operation, a block of user data,
• wherein the block of user data is stored in a first portion of a memory associated with one or more data pins and is retrieved, during the first access operation, using the one or more data pins,
• wherein internal memory error correction code (ECC) information associated with the block of user data is stored in a second portion of the memory associated with one or more data mask inversion (DMI) pins, and
• wherein data transfer via the one or more DMI pins is disabled to enable masked write commands using the one or more DMI pins;
• retrieving, by the memory system controller via a second access operation, cyclic redundancy check (CRC) information associated with the block of user data,
• wherein the CRC information is stored in a third portion of the memory associated with the one or more data pins and is retrieved, during the second access operation, using the one or more data pins;
• and
• determining, by the memory system controller and using the block of user data and the CRC information, whether the block of user data includes one or more bit errors.

A compute express link (CXL) compliant memory system, comprising:

• one or more components configured to:
• retrieve, by a CXL controller and via a first access operation, a user data block (UDB),
• wherein the UDB is stored in a first portion of a dynamic random access memory (DRAM) associated with one or more DQ pins and is retrievable, during the first access operation, using the one or more DQ pins,
• wherein internal memory error correction code (ECC) information associated with the UDB is stored in a second portion of the DRAM associated with one or more data mask inversion (DMI) pins, and
• wherein data transfer via the one or more DMI pins is disabled to enable masked write commands using the one or more DMI pins;
• and
• retrieve, via a second access operation, cyclic redundancy check (CRC) information associated with the UDB,
• wherein the CRC information is stored in a third portion of the DRAM associated with the one or more DQ pins and is retrievable,
• during the second access operation, using the one or more DQ pins.