Memory system and control method
AssigneeKioxia Corporation
InventorsTakahiro KUBOTA, Daiki WATANABE, Kosuke MORINAGA
Life of this patent
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Abstract
A memory controller generates Mi codewords each including a parity with a size Ni, divides each of the parities of the Mi codewords into K partial parities, determines K×A codewords from Mi codewords for Mi write information and the K or less partial parities of the K×A codewords, selects partial parities from the K×A codewords, generates Mi write information including the selected partial parities, and allocates continuous addresses of the nonvolatile memory to the K or less partial parities included in each of the Mi write information. A number of write information with sizes of the included partial parities matched becomes larger.
Claims14
A memory system comprising:
- a memory controller configured to:
- generate Mi codewords by executing error correction coding on data received from a host, Mi being an integer equal to or greater than 2, each of the Mi codewords including a parity with a size Ni, Ni being an integer equal to or greater than 2, for each i being an integer equal to or greater than 1 and equal to or less than I, I being an integer equal to or greater than 1,
- divide each of the parities included in the Mi codewords into K partial parities, K being an integer equal to or greater than 2, each of the K partial parities having a size common to the Mi codewords;
- select K×A codewords from the Mi codewords for each of Mi write information, A being an integer equal to or greater than 1 or more wherein the Mi write information each configured as a unit for writing a nonvolatile memory;
- determine the K or less partial parities from each of the selected K×A codewords;
- select the determined K or less partial parities from the determined K×A codewords and generate the Mi write information each including the selected K or less partial parities;
- and
- allocate continuous addresses of the nonvolatile memory to the K or less partial parities;
- and
- a nonvolatile memory configured to store the Mi write information based on the allocated addresses,
- wherein a number of write information with sizes of the included partial parities matched becomes larger.
A control method of controlling a nonvolatile memory, the method comprising:
- generating Mi codewords by executing error correction coding on user data received from a host, Mi being an integer equal to or greater than 2, each of the Mi codewords including a parity with a size Ni, Ni being equal to or greater than 2 for each i that is an integer being equal to or greater than 1 and equal to or less than I, I being an integer equal to or greater than 1;
- dividing each of the parities included in the Mi codewords into K partial parities, K being an integer equal to or greater than 2, the K partial parities having a common size;
- selecting K×A codewords from the Mi codewords for each of Mi write information, A being an integer equal to or greater than 1, the Mi write information being a unit for writing the nonvolatile memory;
- determining the K or less partial parities from each of the selected K×A codewords;
- selecting the determined K or less partial parities from the determined K×A codewords;
- generating the Mi write information each including the selected K or less parities;
- allocating continuous addresses of the nonvolatile memory to the K or less partial parities included in each of the Mi write information;
- and
- storing the Mi write information based on the allocated addresses in the nonvolatile memory,
- wherein a number of write information with sizes of the included partial parities match becomes larger.
Dependencies are inferred from the claim text.