Memory device including on-die termination circuit, storage controller, and storage device including the same

A memory device, comprising:

• a memory cell array comprising a plurality of memory cells;
• a plurality of page buffers connected to the plurality of memory cells;
• an on-die termination (ODT) circuit including a termination resistor, and configured to perform a termination operation including an ODT enable operation in which the termination resistor connected to a data line through which data are input and output is connected to a power source voltage and an ODT disable operation in which the connection between the termination resistor and the power source voltage is blocked;
• an ODT mode register configured to store an ODT operation mode information on whether the ODT circuit is to perform the termination operation;
• and
• a control logic circuit configured to:
• identify the ODT operation mode information in response to a selection chip enable (SCE) command received from the outside, and
• based on the ODT operation mode information, control the ODT circuit to perform the ODT disable operation, and control the plurality of page buffers to output data stored in the plurality of page buffers to the outside through the data line.

A storage controller, comprising:

• a command queue configured to:
• provide a first read command to a first non-volatile memory device among a plurality of non-volatile memory devices,
• provide an on-die termination (ODT) enable command by which a plurality of ODT circuits included in the plurality of non-volatile memory devices, respectively, are enabled to the plurality of non-volatile memory devices,
• provide a first selection chip enable (SCE) command and a first selection chip termination (SCT) command to the first non-volatile memory device, and
• store a plurality of additional read commands, a plurality of additional SCE commands, and a plurality of additional SCT commands to be provided to remaining non-volatile memory devices excluding the first non-volatile memory device among the plurality of non-volatile memory devices;
• and
• a processor configured to generate an ODT disable command by which the plurality of ODT circuits are disabled based on whether the plurality of additional SCT commands are stored in the command queue.