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US 2026/0029922 A1Published application
Memory controller for use with row-buffer memory
AssigneeAdvanced Micro Devices, Inc.
InventorJames R. Magro
Life of this patent
Estimating the term…
Abstract
A memory controller includes a command queue and an arbiter. The command queue is operable to store a plurality of memory access requests for accessing a row-buffer memory. The arbiter is coupled to the command queue and is operable to pick memory access requests from the command queue for issuance to the row-buffer memory according to a preference for memory access requests that access a data element in a sense amplifier or in a first row buffer of the row-buffer memory.
Claims20
A memory controller, comprising:
- a command queue operable to store a plurality of memory access requests for accessing a row-buffer memory;
- and
- an arbiter coupled to the command queue and operable to pick memory access requests from the command queue for issuance to the row-buffer memory according to a preference for memory access requests that access a data element in a sense amplifier or in a first row buffer of the row-buffer memory.
A data processing system, comprising:
- a data processor comprising a memory controller;
- and
- a row-buffer memory coupled to the memory controller,
- wherein the memory controller comprises:
- a command queue operable to store a plurality of memory access requests for accessing the row-buffer memory;
- and
- an arbiter coupled to the command queue and operable to pick memory access requests from the command queue for issuance to the row-buffer memory according to a preference for memory access requests that access a data element in a sense amplifier or in a first row buffer of the row-buffer memory.
4 more elements
A method of accessing a row-buffer memory by a memory controller, comprising:
- storing a plurality of memory access requests for accessing the row-buffer memory in a command queue;
- picking memory access requests from the command queue according to a preference for memory access requests that access a data element in either a sense amplifier or in a first row buffer of the row-buffer memory;
- and
- issuing picked memory access requests to the row-buffer memory.
1 more element
Dependencies are inferred from the claim text.