Semiconductor device

A semiconductor device comprising:

• a substrate of a first conductivity type;
• a first transistor and a second transistor on the substrate;
• and
• a well region that is between the substrate and the first transistor, and has a second conductivity type different from the first conductivity type, wherein
• the first transistor includes:
• a first channel layer on the substrate;
• a first barrier layer on the first channel layer;
• a first gate electrode on the first barrier layer;
• and
• a first source electrode and a first drain electrode that are on opposite sides of the first gate electrode, and are connected to the first channel layer,
• the second transistor includes:
• a second channel layer on the substrate;
• a second barrier layer on the second channel layer;
• a second gate electrode on the second barrier layer;
• and
• a second source electrode and a second drain electrode that are on opposite sides of the second gate electrode, and are connected to the second channel layer, and
• the first drain electrode is connected to a first power voltage, and the second source electrode is connected to a second power voltage lower than the first power voltage, and wherein the first source electrode and the second drain electrode are connected to the well region.

A semiconductor device comprising:

• a substrate of a first conductivity type;
• a first transistor and a second transistor on the substrate;
• and
• a well region that is between the substrate and the first transistor and has a second conductivity type different from the first conductivity type, wherein
• the first transistor includes:
• a first channel layer on the substrate;
• a first barrier layer on the first channel layer;
• a first gate electrode on the first barrier layer;
• and
• a first source electrode and a first drain electrode that are on opposite sides of the first gate electrode, and are connected to the first channel layer,
• the second transistor includes:
• a second channel layer on the substrate;
• a second barrier layer on the second channel layer;
• a second gate electrode on the second barrier layer;
• and
• a second source electrode and a second drain electrode that are on opposite sides of the second gate electrode, and are connected to the second channel layer,
• the first drain electrode is connected to a first power voltage, and the second source electrode is connected to a second power voltage lower than the first power voltage, and wherein the first source electrode and the second drain electrode are connected to each other,
• the well region includes a first well region between the substrate and the first source electrode and a second well region between the substrate and the first drain electrode, and wherein the first well region and the second well region are spaced apart from each other, and
• the first source electrode is connected to the first well region, and the first drain electrode is connected to the second well region.