Electronic device for transmitting data and correcting error in received data

An electronic memory device, comprising:

• a linear feedback shift register (LFSR) including an N number of exclusive-OR (XOR) gates, an N number of flip-flops, an N number of first switches, an (N-1) number of second switches and a third switch connected between a transmission data input terminal and a transmission CRC code output terminal, wherein the N number of XOR gates, the N number of flip-flops, and the (N-1) number of second switches are connected to each other alternately, where N is a natural number;
• a bit data generator configured to output N-bit data controlling a degree K of a CRC polynomial and K-bit data according to values of a coefficient of the CRC polynomial, where K is a natural number,
• wherein each of the N number of first switches connects the CRC code output terminal to a corresponding XOR gate among the N number of XOR gates in a turned-on state of the first switches,
• wherein each of the (N-1) number of second switches connects an output terminal of a flip-flop of an adjacent preceding stage among the N number of flip-flops to an input terminal of an XOR gate of an adjacent subsequent stage among the N number of XOR gates in a first turned-on state, and connects the output terminal of the flip-flop of the adjacent preceding stage to a first node in a second turned-on state,
• wherein the third switch connects the first node to the CRC code output terminal in a turned-on state, and
• wherein the linear feedback shift register is configured to control states of the N number of first switches, the (N-1) number of second switches, and the third switch, and to derive the transmission CRC code from the transmission data by controlling a state of at least one first switch among the N number of first switches, which is in the turned-on state of the at least one first switch among the N first switches, by the N-bit data.

An electronic memory device, comprising:

• a reception portion configured to receive a plurality of data blocks;
• a data block reassembly portion configured to classify the plurality of data blocks into at least one first data block, a second data block including a reception CRC code corresponding to the first data block, and at least one third data block;
• and
• a CRC decoder configured to generate a comparison CRC code from the first data block, and to determine whether the first data block includes an error by comparing the reception CRC code with the comparison CRC code,
• wherein, when the reception CRC code and the comparison CRC code are not the same, the CRC decoder samples an error position estimation data block including error position estimation data indicative of an estimated position of the error in the first data block, and recalculates the comparison CRC code as a function of the error position estimation data, and
• wherein, when the reception CRC code and the recalculated comparison CRC code are the same, the CRC decoder corrects the error in the first data block as a function of the error position estimation data.