Memory built-in-self-test (mbist) with enhanced fault counter
AssigneeNXP USA, Inc.
InventorsHenning Fritz Spruth, Qadeer Qureshi, Chen He, Kiran K. Thota, Jesse Yanez
Life of this patent
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Abstract
An integrated circuit includes a memory having an array and a memory built-in self test (MBIST) controller. The MBIST controller is configured to perform memory testing rungs on the memory and includes a first counter and a repair control circuit. The first counter is configured to count uncorrectable errors during each memory testing run. The repair control circuit is configured to, in response to an error found during a memory testing run, determine whether at least one of row repair or column repair can be applied to repair the error.
Claims20
An integrated circuit, comprising:
- a memory having an array;
- and
- a memory BIST (MBIST) controller, the MBIST controller configured to perform memory testing runs on the memory, the MBIST controller having:
- a first counter configured to count uncorrectable errors during each memory testing run;
- and
- a repair control circuit configured to, in response to an error found during a memory testing run, determine whether at least one of row repair or column repair can be applied to repair the error.
An integrated circuit, comprising:
- a memory having an array;
- and
- a memory BIST (MBIST) controller, the MBIST controller configured to perform memory testing runs on the memory, each memory testing run including a set of writes to write corresponding test data to the array, a set of reads to obtain corresponding read data from the array, and comparisons between the obtained read data and expected read data to detect occurrences of any hit errors, the MBIST controller having a row repair control register, a column repair control register, and a first counter configured to count uncorrectable errors during each memory testing run, the MBIST controller configured to:
- upon completion of a first memory testing run, configure the column repair control register to apply column repair to repair a first detected bit error;
- reset the first counter prior to commencing a second memory testing run, the second memory testing run is performed while applying column repair to repair the first detected bit error;
- and
- upon completion of a second memory testing run, configure the row repair control register to apply row repair to repair a second detected bit error.
Dependencies are inferred from the claim text.