Analog computing unit for representing negative weights
AssigneeIntelligent HW, Inc.
InventorHwan Jun ZANG
Life of this patent
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AssigneeIntelligent HW, Inc.
InventorHwan Jun ZANG
Estimating the term…
An object is to provide a new analog computing unit capable of reducing the size of an analog computing unit and reducing the amount of power consumption by reducing use of analog-to-digital converters (ADCs) to ¼ as compared to prior arts. In an analog computing unit according to one embodiment, a flash memory cell array included in the unit has the structure in which unlike the prior arts, WLs and CGs are connected in a row direction, and EGs and RLs/BLs are connected in a column direction. Accordingly, the array has the structure in which even-numbered cells for negative weights in a column and odd-numbered cells for positive weights in the column form pairs in a read NN mode, or odd-numbered cells for negative weights in a column and even-numbered cells for positive weights in the column form pairs in a read mode.
An analog computing unit for an artificial neural network comprising
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