Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device comprising:

• forming first source/drain patterns spaced apart from each other in a first direction on a first region of a substrate, and second source/drain patterns spaced apart from each other in the first direction on a second region of the substrate;
• forming first channel patterns between the first source/drain patterns and having a first width in a second direction intersecting the first direction, and second channel patterns between the second source/drain patterns and having a second width in the second direction that is different from the first width;
• forming first internal spaces at least partially surrounded by the first source/drain patterns, and second internal spaces at least partially surrounded by the second source/drain patterns;
• forming a first internal gate spacer on a side surface of a first one of the first source/drain patterns and in a first one of the first internal spaces, and a second internal gate spacer on a side surface of a first one of the second source/drain patterns and in a first one of the second internal spaces, the first internal gate spacer and the second internal gate spacer having a first thickness and a second thickness, respectively, in the first direction;
• and
• forming a first gate electrode in the first internal spaces, and a second gate electrode in the second internal spaces,
• wherein the first thickness of the first internal gate spacer at a center point thereof along the second direction is different from the second thickness of the second internal gate spacer at a center point thereof along the second direction.

A method of manufacturing a semiconductor device comprising:

• forming first source/drain patterns spaced apart from each other in a first direction on a first region of a substrate, and second source/drain patterns spaced apart from each other in the first direction on a second region of the substrate;
• forming first internal spaces at least partially surrounded by first channel patterns between the first source/drain patterns and having a first length in a third direction perpendicular to an upper surface of the substrate, and second internal spaces at least partially surrounded by second channel patterns between the second source/drain patterns and having a second length in the third direction that is different from the first length;
• forming a first internal gate spacer on a side surface of a first one of the first source/drain patterns and in a first one of the first internal spaces, and a second internal gate spacer on a side surface of a first one of the second source/drain patterns and in a first one of the second internal spaces, the first internal gate spacer and the second internal gate spacer having a first thickness and a second thickness, respectively, in the first direction;
• and
• forming a first gate electrode in the first internal spaces, and a second gate electrode in the second internal spaces,
• wherein the first thickness of the first internal gate spacer at a center point thereof along a second direction intersecting the first direction is different from the second thickness of the second internal gate spacer at a center point thereof along the second direction.