Semiconductor devices comprising pillar structure

A semiconductor device, comprising:

• a substrate that comprises a first active pattern and a second active pattern that are spaced apart from each other in a first direction;
• a first channel structure that overlaps the first active pattern in a second direction;
• a first source/drain pattern that is electrically connected to the first channel structure;
• a first pillar structure between the first active pattern and second active pattern;
• and
• a second pillar structure on the first pillar structure,
• wherein the second pillar structure comprises:
• a lower surface in contact with the first pillar structure;
• an upper surface farther than an upper surface of the first source/drain pattern from a lower surface of the substrate in the second direction;
• and
• a first side surface that is on the lower surface of the second pillar structure and on the upper surface of the second pillar structure,
• wherein the first side surface of the second pillar structure is in contact with the first source/drain pattern,
• wherein the first direction is parallel with the lower surface of the substrate, and
• wherein the second direction is perpendicular to the lower surface of the substrate.

A semiconductor device, comprising:

• a substrate that comprises a first active pattern and a second active pattern that are spaced apart from each other in a first direction;
• a first channel structure that overlaps the first active pattern in a second direction;
• a second channel structure that overlaps the second active pattern in the second direction;
• a first gate electrode that overlaps the first active pattern in the first direction and/or the second direction;
• a second gate electrode that overlaps the second active pattern in the first direction and/or the second direction;
• a first source/drain pattern that is electrically connected to the first channel structure;
• a second source/drain pattern that is electrically connected to the second channel structure;
• a first pillar structure between the first channel structure and the second channel structure in the first direction;
• an insulating isolation layer between the first active pattern and the first pillar structure;
• a second pillar structure on the first pillar structure;
• and
• a gate spacer on a side surface of the first gate electrode,
• wherein the gate spacer is between the first pillar structure and the second pillar structure,
• wherein the first direction is parallel with a lower surface of the substrate, and
• wherein the second direction is perpendicular to the lower surface of the substrate.